ADCs play a pivotal role in almost all electronic digital products where analog data must be converted to digital data.  They are vital in data acquisition systems employed in instrumentation, industrial, and medical equipment.  ADCs are a must if there is a need for high dynamic range, high performance, and accurate signal measurements constrained by space restrictions, power, and thermal design challenges.  Multiple types of ADCs are available in the market, and it is recommended that the correct ADC be selected as per application requirements. This article will discuss the key difference between Successive-Approximation Resister (SAR) and Delta Sigma ADC.

 

Successive-Approximation Resister (SAR) ADC

It is the most popular ADC which also happens to be the oldest. The Successive-Approximation Resister ADCs enjoy a resolution from eight to 16 bits, consuming low power in a small form factor. The SAR ADC finds use in high-speed areas and suitable for general purpose applications like data logging, temperature sensors, bridge sensors, industrial control, and instrumentation.

 

 

SAR ADC is implemented on the successive-approximation register (SAR). In simplest terms, a binary search algorithm gets implemented. The successive-approximation algorithm keeps the ADC sample rate comparatively low even though the internal circuitry may run at several megahertz (MHz).

 

Figure 1 shows a SAR ADC  internal circuit where the analog input is fed in a sample-and-hold circuit that samples the input voltage, keeping the voltage constant at the input to the comparator during the conversion process. The SAR ADC has two principal components: the comparator and the digital to analog converter (DAC). An array of registers in parallel imports the output which is then also fed to the DAC. The input voltage range is set by a with a fixed dc reference-voltage connected to the DAC. The DAC output is fed as one input to a comparator, and the other input is the analog signal to be digitized.  When the conversion starts, the switch opens, and the most recent input value gets stored and read by any microcontroller or microprocessor.

 

Delta-Sigma ADC

The practical application of digital signal processing (DSP) led to the development of the delta-sigma (ΔΣ) ADC. When compared to other ADCs, the Delta-Sigma is distinctive and complex but enjoys a better resolution advantage with noise justification. The conversion speed is slower than other ADCs, and applications usually limited to dc and audio frequencies. Instrumentation and digital audio are typical application areas.

 

Figure 2 shows a simple structure of a delta-sigma ADC.  The signal being measured is applied to a differential amplifier in the initial part. The other input of the differential amplifier is DAC output which gets subtracted from the input signal. The difference value is then fed to the integrator and the output result compared to ground. The output of comparator sets or resets the D flip flop (FF) accordingly. The state of the D FF is fed to a 1-bit DAC whose output is either zero or reference voltage.

 

 

This feedback-loop system offers a serial pulse output from the D Flip-Flop producing a binary pulse series whose value is proportional to the input voltage level. One serial bit gets generated on one input signal sample by each clock pulse.

 

Oversampling occurs If the clock rate is considerably higher than the input signal.  The serial output gets further processed in a DSP low-pass filter and a decimator ( a digital filter which discards the unnecessary samples and reduces the data rate to practical value, maintaining the information according to the Nyquist Criterion) resulting in a sequence of fixed bit-length words indicating samples of the input signal. The digital filter and the decimator are implemented as a single unit in the IC.

 

An important feature of the delta-sigma ADC is the elimination of a major chunk of the high frequency quantizing noise generated by the sampling process. The decimation process decreases the number of output words by decimation ratio. The decimation ratio limits the number of data samples from the modulator and is averaged together to get each output word. Greater resolution corresponds to lower output word rate. Delta-sigma ADC is best in high resolution to a maximum of 32 bit.

 

High-performance data acquisition requires a high dynamic range and accurate measurements. Oversampling can achieve this outcome. It helps that the sampling of any input signal process is cost-effective and is done at a notably higher rate compared to the Nyquist frequency. The effective number of bits (ENOB) or resolution and signal-to-noise ratio (SNR) also increase. Oversampling of the ADC by a factor of four provides one additional bit of resolution, or a 6dB increase in dynamic range (DR).

 

Key Differences between SAR and Delta-Sigma ADC

Both ADCs enjoys a maximum sampling rate of 10 Msamples/s. The delta-sigma’s net output data word rate is lower than the sampling rate by the decimation factor and is usually in the ksamples/s range. The noise reduction, however, is greater compared to the SAR.

 

SAR ADCs are popular for their channel multiplexed based architecture requiring fast responses to step input near full-scale amplitude sans any settling time issues. It can be used where multiple inputs are digitized. A multiplexer is placed before the S/H amplifier which selects one input to convert. Each input’s sampling rate is decreased by a factor of the number of inputs. For example, with four inputs and a 4-Msample/s SAR, the maximum sampling rate of each input is 1 Msamples/s.

 

Even though both ADC methods can accurately measure the signals down to DC, then the SAR architecture generally permits the power of the ADC core to scale with the output rate. The power consumption thus reduces by a minimum of 50 percent, thus satisfying the thermal limitations. To compare, a fixed power draw is a characteristic typically attributed to the delta-sigma ADC.

 

In many delta-sigma ADCs, oversampling is integrally implemented with an integrated digital filter, where the modulator clock rate is considerably higher (ranging from 32 to 256 times)  compared to existing signal bandwidth. It is to be noted that oversampling is harder to implement if there is a need for fast switching between the input channels.

 

Noise reduction and anti-aliasing improvement can be achieved by SAR ADC oversampling. Placing a low-pass filter minimize aliasing. The filter additionally limits bandwidth, and the noise consequently gets reduced. The high oversampling ratio and digital filter profile of delta-sigma ADCs minimize the anti-aliasing needs at the analog inputs. Overall noise also gets reduced by oversampling in the ADCs modulator.

 

Oversampling is banned due to the SAR ADC’s high throughput rate. In such cases, achieving a low noise floor with linearity is a must. The low noise floor is achieved by a combination of high throughput and low RMS noise. A few SAR ADCs that have consistently shown high performance provide higher bandwidth, discrete sampling, and high accuracy within a small time frame for fast measurement and control applications. Designers take advantage of low power and fast throughput rate combined with a small packet size to satisfy space, thermal, and other important design challenges common to most high-channel-density systems.

 

SAR architecture sans pipeline delay or latency allows the design of fast control loops. The SAR ADC provides the lowest noise floor compared to the full-scale input floor, with the consequence of superb linearity performance and higher SNR. It is impossible to discard the 1/f noise proximate to DC (50Hz or 60Hz) content, unlike the delta-sigma ADCs.