Having used JFETs (type ) in some of my test circuits whilst experimenting with MOSFETs, I
thought it might be interesting to look at the transfer function and see if I could recreate the curve
you sometimes see on a datasheet which relates the gate voltage to the drain current.
If you're not used to JFETs (Junction Field-Effect Transistors), they're similar to MOSFETs but the
insulation between the gate and the channel is provided not by an actual insulator but rather by a
reverse-biased p-n junction. The immediate effect of that is we need to be careful not to forward-bias
the diode (by raising the gate more than a diode-drop above the source), or at least, if we do, to
ensure that the current that flows is suitably limited. Operation of the device is then in the region
down from that diode-drop voltage to whatever negative voltage (negative relative to the source) it
takes to close off the channel. [I'm referring to n-channel parts here - reverse all the voltages for a
This is what a typical curve might look like. I've taken this from an old app note  because the JFET
I'm going to be measuring doesn't have any curves at all on the datasheet.
There are several parameters we might be interested in that we could take from the curve. One of those
is the zero-voltage current (the drain current when the gate-source voltage is zero), though that could
be easily measured in other ways. Another parameter of interest is the negative voltage where the
current falls to zero. A little less obviously, we could get the incremental transconductance from the
slope of the curve at a particular gate voltage.
The app note I mentioned above is for a tester that does the same as what I'm trying to do here. I
didn't discover it until part-way through, so the detail of mine is somewhat different, although the
basic principle of operation is similar. If you wanted to build one, you might do better with theirs as
it handles n-type and p-type devices; mine is just suitable for the n-type parts that I had available to
Here's the circuit I came up with. The JFET I've got as the 'device under test' [DUT] was just an
arbitrary choice from the ones in the simulation library. The part I'm testing doesn't seem to
have a spice model.
The heart of it is an op-amp integrator that generates the ramping voltage that's applied to the gate.
That voltage is a downwards ramp, from zero to about -6V. To reset it, I have a simple pulse generator
that turns on a MOSFET across the integration capacitor. That periodically discharges the capacitor.
It's not all that elegant, but I'm only throwing it together for an experiment.
On the output side, the drain of the JFET has a resistor to convert the output current to a voltage and
then there's a differential amplifier to shift it down so that it's ground-referenced for the 'scope
probe to measure.
Here it is built on a breadboard:
I had a couple of problems with it. One simple one was that the reset didn't take the ramp back to zero
voltage, but left an offset of about -100mV at the gate. That was a shame as it stops us looking at the
zero-volt current so, instead of taking the non-inverting input to ground, I lifted it with a diode
The other problem was that the integrator 'sang' a bit. There was a low level of 1MHz oscillation on the
ramp. I dealt with that by increasing the size of the integrator capacitor by a factor of ten (and
dropping the charging resistor by the same factor) [originally I had 47nF and 47k for the two]. That has
the effect of rolling-off the gain faster, which I suppose is why it cut out most of it, but you can
still see the effect slightly along the top of the ramp waveform. That might well be down to using the
breadboard [capacitance between the strips of contacts], but I can live with it for the purposes of this
Here are the results I get when testing a part.
This shows the gate ramp voltage [yellow] and the drain current [blue]. You can see where the pulse
generator does the reset back up to just above zero. The drain current is 100mV = 1mA, so on the
following trace we have 2mA per division.
Here it is in more detail.
Finally, this is what it looks like if I get the 'scope to plot it XY, where we see it in the more
traditional form. The spread at the top is due to the slight oscillation I just mentioned.
The scale up is 2mA per division, so the zero-volt current is about 9mA. That's in the middle of the
range given by the datasheet [6mA to 13mA]. The cut-off is harder to measure because my circuit isn't
very good (there's a small offset on the current measurement) and it's difficult to see where it gets to
zero. It looks like it may be around -2.7V.
The one feature that's slightly surprising is the transconductance. By eye, the transconductance at zero
looks to be roughly about 4.5mS (9mA/2V), but that's the minimum value given on the datasheet. Perhaps
it's down to the drain voltage (the datasheet uses 15V, but I've only got the 9V of the supply, less a
volt for the current sense).
Although it quickly showed up the limitations of the breadboard, otherwise it worked reasonably well as
an experiment. If I have some time I'll measure a selection of parts and see how much spread there
is to the zero-voltage current and the cut-off point.
 Fairchild application note AN-6610 https://www.onsemi.com/pub/Collateral/AN-6610.pdf.pdf
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