More experimenting. This time I thought I'd have a look at the output characteristics of a JFET. Sometimes these

things go well and sometimes they don't. This one didn't go too well but, for all that, I'm going to blog it as I did

it rather than try and tidy it up.


The output characteristic is how the drain current behaves with changing drain voltage and is usually shown for a

series of fixed gate voltages. Here is an example from a datasheet. This is for a 2SK3557 part (the datasheet I have

for the BF256BBF256B parts, that I'm actually going to measure, doesn't show these curves).




People have different names for the two main regions.


The flattish top is sometimes called the 'saturation region' (the mechanism isn't the same as saturation for a BJT

[Bipolar Junction Transistor], so the terminology gets a little confusing), but you'll also see 'active region' used.

Here the JFET is acting to regulate the current. The top isn't perfectly level, so it isn't a perfect current source.

Operating in this region is where we'd be if we were using the JFET as an amplifier.


The run up to it is often called the 'ohmic region', though you might also see 'triode region' in older books (by

analogy with vacuum tubes, which engineers would have been very familiar with when JFETs and MOSFETs were first

introduced), and also, to my mind somewhat confusingly, 'linear region'. Here the gate is controlling the resistance

of the channel. It's not a particularly good resistor as, once the drain voltage starts to rise, you can see it

slopes away from proportionality between voltage and current quite quickly. In practical circuits, that region

sometimes gets used as a voltage-controlled resistance - one example would be in an application like AGC [Automatic Gain



Circuit and Build


Here's the circuit I came up with. If you've been following my series of blogs experimenting with semiconductors,

you'll quickly realise that most of this one is built from elements of previous circuits. In theory, taking what

you've already done and reworking it can be a good, efficient way to work but, in this case, it gave me a couple of

problems that I've yet to sort out.



In order to draw the curves on the oscilloscope, I first need a way to set the gate voltage and then I need to sweep

the drain voltage whilst monitoring the current. Setting the gate voltage I can do with a variation on the R-2R

ladder network DAC [Digital to Analogue Converter], controlled by an Arduino Uno, that I've used before. To get the

negative voltages for the gate, I'm simply going to invert the positive voltage out of the DAC with an op amp set up

as an inverting amplifier. I'll adjust the gain of the inverting amplifier to give me steps of -0.1V down from 0V.


It probably won't be obvious, from looking at the circuit, how I derived the values for the gain-setting resistors.

The input resistor R14 loads the resistor network, so we can't treat it simply as a high impedance that doesn't have

any effect. The key is that a curious feature of this ladder network is that the resistance looking back into the

output is simply the value of one of the resistors that make it up, in this case 10k, so the DAC looks like a voltage

source in series with a 10k resistor [that's not quite, strictly, accurate because we should also take into account

the on resistance of the MOSFETs in the UNO drivers, but since they are probably in the area of 25 ohms, or so, they

don't make much difference to the 10k figure in practice]. It's curious, because it applies however the inputs are

switched. The voltage source steps in increments of 5V x 1/16 = 0.3125V, so the rest is straightforward (assuming you

know op amp design and can design an inverting amplifier).


The drain voltage I'm going to set using a source-follower MOSFET controlled by an op amp. The op amp will keep the

drain voltage the same as the voltage at its non-inverting input. That voltage comes from capacitor C1 being charged

by a constant-current source made up of T3. Charging a capacitor with a fixed constant current should give me a

linear ramp voltage. Well, sort of. The ramp isn't spectacularly linear, but I'm hoping it will be good enough. The

ramp gets reset by the UNO using T1 and T2 to get it back to zero, ready for the next run with a different gate



The current I'll measure with a 100 ohm current-sense resistor (R23), buffered by an op amp working as a differential

amplifier. That then gives me a ground-referenced output for the oscilloscope. I used a MOSFET to buffer U1's output

so that the current seen by the current sense would be the same as the current in the drain of the FET under test.

This isn't a precision circuit and if you were serious about getting good curves it would need much improvement but,

as a quick hack to get an idea of the curves, it should do me fine.


Here it is breadboarded on a piece of scrap pcb material. That board has already been used for a couple of the other

experiments, so it's getting slightly messy. If I was creating it from scratch, the layout would probably be much






Testing a BF256BBF256B


Here's a test of the gate drive. That's generated by the UNO stepping A3-A0 from 0 to 10, which gives me 0V down to

-1.0V at the gate. Not too bad. Good glitches when the UNO outputs switch (but fear not, they're well away from the




Now, here are the results I get when testing a BF256BBF256B part:



I changed the UNO code so that the gate drive would be stepped in increments of -0.2V, from 0V down to -1.4V.


I haven't tried to show this XY because the oscilloscope makes a complete mess of displaying it, however, on this

timebase setting, the drain voltage ramp [yellow trace] equates to one division per volt across the screen so it will

do much the same job. The drain current [blue trace] is 100mV per mA [so 2mA per vertical division].


The top trace is for Vgs=0V and the bottom one is -1.4V.


Although it shows the curves, it also shows two major problems with my circuit. There's a considerable offset from

0mA on the current sensing and the op amp can't keep up during the initial change in the drain current. Part of the

problem is that I'm trying to do this too fast, which is a hangover from the power MOSFET circuits where it was

necessary to work very fast because of the power dissipation problems. But, also, I'm probably expecting a bit too

much of a humble LM324 device which doesn't even pretend to be a precision part.


Update 4th Feb 2020.


The issue with the fast speed at which I was doing the test came from reusing an old board. I had made the mistake of not checking the value of C1 and it turned out it wasn't the 470nF I've got on the circuit (it was much less). After changing that, I got this



You can see the lift off is much smoother now and doesn't wobble around. Now I can see better what happens at the bottom end and the reason for the discrepancy on the current reading: the drain voltage doesn't get down to zero. That's because of the saturation voltage of the transistor that discharges the ramp capacitor. Simplest thing to do was to swap it for a MOSFET (I used a BS170).


That then gave me this. It's still noisy, but the curves are more or less where they should be now. The top curve is for Vgs=0V. I measured that one at DC with a meter and it read 9mA at 15V Vds, so the current sensing looks reasonably accurate.



The result of all that was to give me something I could then display successfully XY on the oscilloscope. Here are two views.

The second shows the start of the curves in a little more detail. The vertical scale is 2mA/div. The top curve is for Vgs = 0V,

then they step down in intervals of -0.2V until we get to Vgs = -1.4V as the bottom curve.






Must try harder!


[1] Integrated Electronics. Millman, J & Halkias, C. C. McGraw-Hill. 1972.
[2] Transistor Circuit Techniques: Discrete and Integrated. Richie, G.J. Van Nostrand Reinhold. 1983.
[3] Advanced Electronic Circuit Design. Comer, D. & Comer, D. John Wiley & Sons. 2003.


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