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    Cortex-R4 Overview


    The Cortex™-R4 processor is the first deeply embedded real-time processor to be based on the ARMv7-R architecture. It is intended for use in high-volume deeply-embedded System-on-Chip applications such as hard disk drive controllers, wireless baseband processors, consumer products and electronic control units for automotive systems.


    Cortex-R4 delivers substantially higher performance, real-time responsiveness and more features than other processors in its class. This processor offers excellent energy efficiency and cost effectiveness for ASIC, ASSP and MCU embedded applications. Furthermore, the Cortex-R4 processor can be configured at synthesis time to optimize its feature set for a precise match with application requirements.







    Eight-stage pipeline with instruction pre-fetch, branch   prediction and selected dual-issue execution. Parallel execution paths for   load-store, MAC, shift-ALU, divide and floating point. 1.66 Dhrystone   MIPS/MHz. Hardware divider. Binary compatibility with classic ARM9 and ARM11   embedded processors.

    Instruction Set

    ARMv7-R architecture with Thumb-2 and thumb. DSP   extensions. Optional floating point unit.

    Cache controllers

    Harvard memory architecture with optional integrated   Instruction and Data cache controllers. Cache sizes configurable from 4 to 64   KB. Cache lines are either write-back or write-through.

    Tightly-Coupled Memories

    Optional Tightly-Coupled Memory interfaces. TCMs are used   for highly deterministic or low-latency applications that may not respond   well to caching, e.g. instruction code for interrupt service routines and   data that requires intense processing. One or two logical TCMs, A and B, can   be used for any mix of code and data.  TCM size can be up to 8 MB. TCM B   has two physical ports, B0 and B1, for interleaving incoming DMA data   streams.

    Interrupt interface

    Standard interrupt, IRQ, and non-maskable fast interrupt,   FIQ, inputs are provided together with a VIC interrupt controller vector   port. The GIC interrupt controller can also be used if more complex   priority-based interrupt handling is required. The processor includes   low-latency interrupt technology which allows long multi-cycle instructions   to interrupted and restarted. Lengthy memory accesses are also deferred in   certain circumstances. Worst case interrupt response can be as low as   20-cycles using the FIQ alone.

    Memory Protection Unit

    Optional MPU configures attributes for either eight or   twelve regions, each with resolution down to 32 Bytes. Regions can overlap,   and the highest numbered region has highest priority.

    Floating Point Unit

    Optional Floating Point Unit (FPU) implements the ARM   Vector Floating Point architecture VFPv3 with 16 double-precision registers,   compliant with IEEE754. The FPU performance is optimized for single-precision   calculations and it also has full support for double-precision. Operations   include add, subtract, multiply, divide, multiply and accumulate, square   root, conversions between fixed and floating-point, and floating-point   constant instructions.


    Optional single-bit error correction and two-bit error   detection for cache and/or TCM memories with ECC bits. Single-bit soft errors   are automatically corrected by the processor.


    Optional support for parity bit error detection in caches   and/or TCMs.

    Master AXI bus

    64-bit AMBA AXI bus master for Level-2 memory and   peripheral access.

    Slave AXI bus

    Optional 64-bit AMBA AXI bus slave port allows DMA masters   to access the dual-port TCM B interface for high speed streaming of data in   and out of the processor.


    Debug Access Port is provided. Its functionality can be   extended with DK-R4.


    An interface suitable for connection to CoreSight Embedded   Trace Module is present.

    Dual core

    A dual processor configuration implements a redundant   Cortex-R4 CPU in lock-step with offset clocks and comparison logic for fault   tolerant/fault detecting dependable systems.


    Synthesizable Verilog RTL with facility to configure options for synthesis




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