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    Cortex-M0+ Overview

     

    ARMCM0+.jpgThe ARM Cortex™-M0+ processor is the most energy efficient ARM processor available. It builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance. Along with the Cortex-M0 processor, the exceptionally small silicon area, low power and minimal code footprint of these processors enable developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.

     

     

    An optimized architecture with a core pipeline of just two stages, enables the Cortex-M0+ processor to achieve a power consumption of just 11.2uW/MHz (90LP process, minimal configuration), while raising the performance to 1.77 CoreMark/MHz.

     

     

    Features:

     

    • 2-stage pipeline enabling faster branch instruction execution with fewer clock cycles and minimizes power consumption
    • 2x to 10x more performance than legacy 8- and 16-bit architectures
    • World leading energy efficiency, maximizing battery life and enabling smaller, lighter applications
    • Single-cycle I/O and peripheral access improve reaction time to external events
    • Linear 4 GB address space removes complex paging schemes, simplifying software architecture
    • Excellent code density reduces flash size needed for a given application while outperforming 8-bit and 16-bit counterparts
    • A micro trace buffer provides a simple, low-cost debugging solution that allows faster bug identification and correction without the need for additional I/O resources
    • Upward compatible with Cortex-M3/4 cores and downward compatible to Cortex-M0 core. Broad ARM ecosystem support


     

     

    Ease-of-use

     

    • Cortex-M compatibility – 100% compatible with Cortex-M0 instruction set and a subset the Cortex-M3/M4 instruction set, allows reuse of existing compilers and debug tools minimising migration effort
    • Simplified architecture with 8-bit look & feel – only 56 instructions and 17 registers, enables easy programming and efficient packaging of 8/16/32-bit data in memory
    • Linear 4 GB address space - removes the need for paging/banking, reducing software complexity
    • Nested Vectored Interrupt Controller (NVIC) – manages interrupt prioritisation, masking and nested interrupt handling
    • Micro trace buffer – provides a light weight trace solution that allows faster bug identification and correction without the need for additional I/O resources
    • Supported by the extensive ARM 3rd party ecosystem – large range of off-the-shelf software and tools help minimise development time/cost

     

     

     

    Energy Efficiency

     

    • More than 2x CoreMark/mA performance than the closest 8/16-bit competitor and 30% less power consumption than Cortex-M0
    • 2x to 40x more performance than 8- and 16-bit and 9% more performance than Cortex-M0
    • Fast I/O port – single-cycle access to I/O and critical peripherals (up to 50% faster than normal I/O), improves reaction time to external events allowing bit-banding and software protocol emulation
    • 2-stage pipeline – reduced number of cycles per instruction (CPI) enables faster branch instruction and ISR entry, reduced power consumption and increased performance
    • Optimized access to program memory – accesses on alternate cycles reduces power consumption
    • Excellent code density vs. 8-bit and 16-bit architectures – reduced flash size, system cost and power consumption for a given application while delivering significantly higher performance

     

     


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