|Technical Documents||Video||Features||Kit Contents|
The Analog Devices circuit is a wideband receiver front end based on the ultralow noise differential amplifier driver and the 16-bit, 250 MSPS analog-to-digital converter.
The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 1.8 dB. The overall circuit has a bandwidth of 152 MHz with a pass band flatness of 1 dB. The SNR and SFDR measured with a 120 MHz analog input are 72.6 dBFS and 82.2 dBc, respectively.
The circuit accepts a single-ended input and converts it to differential using a wide bandwidth (3 GHz) M/A-COM ECT1-1-13M 1:1 transformer. The 3.3 GHz differential amplifier has a differential input impedance of 400 Ω when operating at a gain of 6 dB and 200 Ω when operating at a gain of 12 dB. A gain option of 15.5 dB is also available.
The is an ideal driver for the , and the fully differential architecture through the low-pass filter and into the ADC provides good high frequency common-mode rejection, as well as minimizes second-order distortion products.
This circuit uses a modified circuit board and the FPGA-based data capture board. The two boards have mating high speed connectors, allowing for the quick setup and evaluation of the circuit’s performance. Modifications made to EVAL-AD9467-250EBZ Evaluation Board include that the ADL5562 and some of its supporting components have been already installed. However, in order to engage this active signal path including the lowpass filter some R/L/C components were added, removed or changed.
Key Applications: Communications, Radar
|Schematics||ADI: Schematics for CN0227 Evaluation Board|
|BOM||ADI: BOM File for CN0227 Evaluation Board|
|Layout||ADI: Layout File for AD9467|
|Reference Design||ADI: Reference Design for AD9467 Evaluation Board, ADC-FMC Interposer and Xilinx|
|Reference Design||ADI: Reference Design for AD9467 Native FMC Card / Xilinx Reference Design|
|Simulation Model||ADI: IBIS Model for AD9467BSV (Valid for All Speeds)|
Key Features for are as below:
- 75.5 dBFS SNR to 210 MHz at 250 MSPS
- 90 dBFS SFDR to 300 MHz at 250 MSPS
- SFDR at 170 MHz at 250 MSPS
- 92 dBFS at −1 dBFS
- 100 dBFS at −2 dBFS
- 60 fs rms jitter
- Excellent linearity at 250 MSPS
- DNL = ±0.5 LSB typical
- INL = ±3.5 LSB typical
- 2 V p-p to 2.5 V p-p (default) differential full-scale input (programmable)
- Integrated input buffer
- External reference support option
- Clock duty cycle stabilizer
- Output clock available
- Serial port control
- Built-in selectable digital test pattern generation
- Selectable output data format
- LVDS outputs (ANSI-644 compatible)
- 1.8 V and 3.3 V supply operation
The Analog Devices Evaluation Board is supplied with below contents:
- Evaluation Board