Version 18
    Texas Instruments > Data Conversion > Analog to Digital Converter >
    • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
    • Easy to use software GUI to configure the ADS42JB69 and LMK04828 for a variety of configurations through a USB interface
    • Quickly evaluate ADC performance through High Speed Data Converter Pro software
    • Simple connection to TSW1400EVM capture card via JESD204B translator card (see ADS42JB69SEK) or direct connection to FMC based Xilinx development platform

     

    The ADS42JB69EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS42JB69 and LMK04828 clock jitter cleaner. The ADS42JB69 is a low power, 16-bit, 250-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface. The EVM has transformer coupled analog inputs to accommodate a wide range of signal sources and frequencies. The LMK04828 provides an ultra-low-jitter and phase noise ADC sample clock along with System Reference clocks and Device Sample clock for a complete JESD204B subclass 1 clocking solution.

    The ADS42JB69 and LMK04828 are controlled through an easy to use software GUI to enable quick configuration for a variety of uses.

    The ADS42JB69EVM will connect directly to the FMC port of the Xilinx’s KC705 evaluation platform. TI also has an ADS42JB69SEK which includes the ADS42JB69EVM and a JESD204B translator card allowing a direct connection to the TSW1400EVM data capture card.

    The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.