The TSW14J56 Evaluation Module (EVM) is a next generation of pattern generator and data capture card used to evaluate performances of the Texas Instruments (TI) JESD204B family of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC).
Populated with an Arria V GZ device and using Altera’s JESD204B IP solution, the TSW14J56 can be dynamically configurable to support all lanes speeds from 600Mbps to 10.3125Gbps, from 1 to 8 lanes, 1 to 16 converters, and 1 to 4 octets per frame.
Together with the accompanying High Speed Data Converter Pro Graphic User Interface (GUI), it is a complete system that captures and evaluates data samples from ADC EVM’s and generates and sends desired test patterns to DAC EVM’s.
The TSW14J56EVM has a single industry standard FMC connector that interfaces directly with TI JESD204B ADC and DAC EVM's. When used with an ADC EVM, high-speed serial data is captured, deserialized and formatted by an Altera Arria V GZ FPGA. The data is then stored into an external DDR3 memory bank, enabling the TSW14J56 to store up to 512M 16-bit data samples. To acquire data on a host PC, the FPGA reads the data from memory and transmits it on a serial peripheral interface (SPI). An onboard high-speed USB-to-SPI converter bridges the FPGA SPI interface to the host PC and GUI.
In pattern generator mode, the TSW14J56 generates desired test patterns for DAC EVMs under test. These patterns are sent from the host PC over the USB interface to the TSW14J56. The FPGA stores the data received into the board DDR3 memory module. The data from memory is then read by the FPGA and transmitted to a DAC EVM across the JESD204B interface connector. The board contains a 100-MHz oscillator used to generate the DDR3 reference clock and a 10-MHz oscillator for general purpose use.
- Quickly evaluate JESD204B DAC and ADC performance using TI High Speed Data Converter Pro software
- Direct connection to all TI JESD204B High Speed Data Converter EVM’s using an FMC standard connector
- Quarter rate DDR3 controllers supporting up to 800MHz DDR3 operation
- JESD RX and TX IP cores with 10 routed transceiver channels
- Many available general purpose IO’s (status signals, SPI interface, etc.) between the FPGA and the FMC connector
- SPI/JTAG reconfigurable JESD core parameters: L,M,K,F,HD,S etc.
- Support for SUBCLASS 0 and 1 operation
- Dynamically reconfigurable transceiver data rate using HSDC Pro software.
- Operating range from 0.611Gbps to 10.3125Gbps
- 8Gb x64 DDR3 SDRAM (split into two independent x32 4Gb SDRAMs, total of 256M 16-bit samples each)
- Evaluation Board