This file contains Verilog source code, user constraint files, and bitstreams for John Beetem's LOGI 'blogs.
This design is licensed under the Creative Commons Attribution-ShareAlike 3.0 Unported License. To view a copy of this license, visit creativecommons.org/licenses/by-sa/3.0/. No warranty is expressed or implied.
Update 7 Oct 2014: added LOGI-Pi source and bitstreams.
Update 12 Oct 2014: added LOGI-EDU seven-segment BCD counter source and bitstreams.