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Using Python Overlays to Experiment with Neural Networks

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Description

 

Utilizing PYNQ (Python Productivity for Zynq) from Xilinx and the Avnet Ultra96-V2 Single Board Computer

 

Summary

 

Python Productivity for Zynq, or PYNQ, has the ability to present programmable logic circuits as hardware libraries called overlays. These overlays are analogous to software libraries. A software engineer can select the overlay that best matches their application. The overlay can be accessed through an application programming interface (API). Using existing community overlays, this course will examine how a beginner can experiment with neural networks using PYNQ on Ultra96. The course will then point you to the best resources to begin your own PYNQ journey!

 

What You Will Learn In This Webinar:

 

  • Understand what PYNQ and PYNQ overlays are
  • Learn how to set up Ultra96-V2 to boot and use PYNQ See both binary and quantized neural network examples running with PYNQ on Ultra96-V2 Explore the best avenues to get started with PYNQ and Ultra96-V2
  • See both binary and quantized neural network examples running with PYNQ on Ultra96-V2
  • Explore the best avenues to get started with PYNQ and Ultra96-V2

 

About the Ultra96-V2:

 

Like Ultra96, the Ultra96-V2 is an Arm-based, Xilinx Zynq UltraScale+ ™ MPSoC development board based on the Linaro 96Boards Consumer Edition (CE) specification. Ultra96-V2 is available in more countries around the world as it has been designed with a certified radio module from Microchip. Engineers have options of connecting to Ultra96-V2 through a Webserver using integrated wireless access point capability or to use the provided PetaLinux desktop environment which can be viewed on the integrated Mini DisplayPort video output. Multiple application examples and on-board development options are provided as examples.

 

Ultra96-V2 provides four user-controllable LEDs. Engineers may also interact with the board through the 96Boards-compatible low-speed and high-speed expansion connectors by adding peripheral accessories such as those included in the MikroE Click Mezzanine for 96Boards (available as an accessory). Micron LPDDR4 memory provides 2 GB of RAM in a 512M x 32 configuration. Wireless options include 802.11b/g/n Wi-Fi and Bluetooth 5 Low Energy. The radio module is Agency Certified in over 75 countries. UARTs are accessible on a header as well as through the expansion connector. JTAG is available through a header. The convenient JTAG/UART Pod (available as an accessory) provides both JTAG and UART connections via USB. I2C is available through the expansion connector. Two Microchip USB3320 USB 2.0 ULPI Transceivers and one Microchip USB5744 4-Port SS/HS USB Controller Hub enable multiple USB connections. Ultra96-V2 provides one upstream (device) and two downstream (host) USB 3.0 connections. A USB 2.0 downstream (host) interface is provided via the high-speed expansion. An IDT VersaClock 6E clock generator provides timing for USB 3.0, USB 2.0, DisplayPort, and the Xilinx MPSoC primary clock input. The integrated Infineon programmable power regulators generate all on-board voltages from an external 12V supply (available as an accessory) as well as providing access to power telemetry through PMBus connectivity.

 

Features

  • Xilinx Zynq UltraScale+ MPSoC ZU3EG A484
  • Micron 2 GB (512M x32) LPDDR4 Memory
  • Delkin 16 GB microSD card + adapter
  • PetaLinux environment available for download
  • Microchip Wi-Fi / Bluetooth
  • IDT VersaClock 6E clock generator
  • Infineon high efficiency power management
  • Aavid/Boyd Heatsink
  • Mini DisplayPort (MiniDP or mDP
  • 1x USB 3.0 Type Micro-B upstream port
  • 2x USB 3.0, 1x USB 2.0 Type A downstream ports
  • 40-pin 96Boards Low-speed expansion header
  • 60-pin 96Boards High-speed expansion header
  • 85mm x 54mm form factor
  • Linaro 96Boards Consumer Edition compatible

 

Target Applications

  • Artificial Intelligence
  • Machine Learning
  • IoT/Cloud connectivity for add-on sensors
  • Embedded Computing
  • Robotic
  • Entry level Zynq UltraScale+ MPSoC development environment
  • Training, prototyping and proof of-concept demo platform
  • Wireless design and demonstrations using Wi-Fi and Bluetooth

 

The Presenters:

 

Bryan Fletcher , Technical Marketing Director, AvnetFred Kellerman, Wireless Edge Communication Systems Architect, Avnet
I've been a fan of programmable logic technology since early in my career at Hewlett-Packard and Evans & Sutherland. I work now in Avnet's Products & Emerging Technologies group, currently working on Ultra96-V2, after working on many development boards over the years and as a Field Applications Engineer.I have extensive experience with software system development for Xilinx RFSoC, MPSoC, DSP, FPGA and multi-processor real-time embedded and digital wireless communication systems. I have had many opportunities to give technical presentations and teach at RIT for the EE department. I program with C / C++ / Python / Matlab and VHDL . Currently I am working with Avnet and Xlinx to integrate their ACAP, MPSoC and RFSoC ICs into 5G cellular beamforming and other communication systems. I worked with Avnet and Xilinx to help nurture their open source Python productivity for ZYNQ framework ( PYNQ ) specifically for the Avnet / Xilinx Ultra96 platform.

When and Where

  • Start Time:

    Apr 8, 2020 11:00 AM CDT (America/Chicago)
  • End Time:

    Apr 8, 2020 12:00 PM CDT (America/Chicago)
  • Location:

    On24

Event Info

  • Event Type:

    Webinar
  • Event Visibility & Attendance Policy:

    Open

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