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The Vivado Design Suite from Xilinx offers tools and methodologies to speed up FPGA development, while improving productivity. Within Vivado, developers can leverage C-based design, capture, simulate and implement programmable logic designs targeting Xilinx FPGA and SoCs (System-on-Chips).
This three-session introduction to Xilinx Vivado Design Suite will examine how we capture designs in Vivado using both RTL entry and IP Integrator. Following design capture we will examine Vivado’s simulation capabilities that help ensure the performance of the captured design aligns with requirements. When we reach the desired functional performance level, we will move on to design implementation and programming file creation for deployment.
Just as with real life, our journey does not end there. We will also explore how we can debug the implemented design on the device as it is integrated into the wider system, should the need occur.
Each workshop session will walk you through everything you need to know to go from a Zero to a Hero using Vivado. Adam Taylor will walk you through everything you need to know to get started using Vivado. Like the previous PYNQ course we will provide examples, and as the series progresses build onto what we've learned. No board is required.
In this session we will look more closely at more commonly used features which enable designs to be generated faster.
Topics covered include:
- IP Integrator – Reduce the RTL you need to write and accelerate your design
- Constraints – What is there role in the design, how do we use them?
- Timing Analysis – What is timing closure, why is it important, and how do we achieve it?
- Programming Configuration Memories
Dates and Register for Free:
When and Where
Start Time:Sep 2, 2020 10:30 AM CDT (America/Chicago)
End Time:Sep 2, 2020 11:30 AM CDT (America/Chicago)
Event Visibility & Attendance Policy:Open
- tariq.ahmad (Owner)