Event has ended
Power integrity issues may create intermittent failures in FPGAs by affecting the internal timing of digital logic and the signal integrity of the high speed interfaces between FPGA and external components, like for example an external DDR memory bank.
This webinar starts with the fundamental concepts of power integrity and then it narrows the focus to the specifics of FPGA designs. The theoretical concepts are then exemplified with measurements and simulations. Part of these experiments the FPGA is programmed to function as an electronic load for its own power supply and then it drives DC and transient pulse currents through the power distribution network. The transient step response is then used to analyze the voltage regulator control loop stability.
Also part of these experiments the FPGA is programmed to operate as a Vector Network Analyzer (VNA) for its own power distribution network and the measured frequency response and s-parameters are used to analyze and simulate the power supply noise as seen by the logic circuits on the FPGA. The signal integrity on an FPGA DDR memory interface is also analyzed through theory and experiments.
- Fundamentals of power integrity in FPGA systems
- Mechanisms of system failures
- Testing the FPGA power supply through transient step response
- Testing the FPGA power supply through frequency response
- Evaluating the efficiency of decoupling capacitors
- Power integrity effects on signal integrity
- example analysis on a DDR3 FPGA memory interface
Cosmin Iorga, element14 Community Member
Cosmin Iorga brings 25 years of industry experience in signal integrity, power integrity, noise coupling, and circuit design at chip, package, and PCB levels. Cosmin has earned his PhD in Electrical Engineering from Stanford University and he is the author of the book "Noise Coupling in Integrated Circuits - A Practical Approach to Analysis, Modeling, and Suppression". Cosmin teaches courses in circuit design, power integrity and noise coupling at UCLA Extension.
When and Where
Start Time:Oct 20, 2021 2:00 PM CDT (America/Chicago)
End Time:Oct 20, 2021 3:00 PM CDT (America/Chicago)
Event Visibility & Attendance Policy:Open
- tariq.ahmad (Owner)