First, I would like to thank element14 for providing me one of the ten boards for the Arty-s7 series webinar. I was glad to be a part of the webinar and attended all three. I was also learning FPGA because of their several advantages and flexibility they provide. When I started, I just had thought that FPGA's can emulate the Microcontrollers. It can just become a microcontroller with users loading .bitstream file onto them, which contains the entire complied design of a Microcontroller. It also has many advantages and features to offer. I would like to list some of the advantages of FPGA's.


The webinars for Arty-s7 had three parts:

  • Installing the Vivado design suite and Xilinx tools
  • Running the hello world application on the Arty-s7 board
  • Interfacing P-mod(peripheral module) IP sensor to one of the P-mod connector


The Arty-s7 comes with Spartan-7 FPGA from Xilinx. The spartan FPGA from Xilinx provides many latest features and supports Vivado 2017.3 and newer. It has Arduino connectors and also P-mod connectors for a more streamlined design experience. Arty-s7 is designed to be Microblaze ready and comes with ready to use free Xilinx webpack licensing with the Vivado design suite.



The Installation of the Vivado is not that trivial. You can also choose between Windows or Linux platforms.

There could be a larger download depending on the packages you select.


The first webinar was about the installation of Vivado. The second part was about running the basic Hello_world program.

In this blog, I will first explain how I have run the last project, which was about interfacing and accessing sensor values from the P_mod_NAV sensor.


For Lab3 the first step was to start the Vivado IDE and make a design with Microblaze.

The Lab2 has already explained in detail the design with Microblaz and run the hello_world application.

So when you open the Vivado your Block diagram should look something like the following screenshot.

The next step is to install the IP's(Intelectual Property) from the repository.

These IP's will have block and design files, as well as documentation for each of the IP's, downloaded in a .zip file. library/archive/



Next, go to the Project->Settings->IP->Repository and click on the + icon and navigate to the downloaded repository containing IPs.

This will add about 66 IP's and 4 Interfaces.


Now, it is time to edit the block design and add the P-Mod_NAV block into the existing Microblaze design and make the necessary connections.

First, add the block by clicking on the + icon and searching for the pmodNAV. Then run the connection automation which will automatically connect the Pmod_NAV to the Microblaze design.

Then connect all the interrupts as shown in the lab_3 pdf(step15).


The final block design should look like the following.



The next step will be to validate the block design and generate the bitstream. Once the bitstream has been generated, a window will open with few options. Click on cancel.

Next, go to the File->Export Hardware, then click yes to overwrite the module file.


Next, Launch Vitis IDE from the tools->Launch Vitis IDE menu.

Create a new application named lab3. Click next

Then go the create a new platform from hardware and select the newly created .xsa file.

Create an empty application and click finish.




Now, the Lab3 download from the webinar link already contains the main file to be used to run the example code. Copy that file to the newly created Vitis application.

In the /src folder you should be able to see the main.c file.

Next, open the file in Vitis IDE.

Next, open the terminal to view the output.

Then connect the Pmod_NAV in the JA connector.

select P-modnav_ststem from Vitis IDE and click on Build.

select from the Xilinx-> Program FPGA.


Then Run->Run As-> Launch Hardware to view the sensor values.