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PCB stack-up design

Posted by skipbruce Aug 21, 2014
PCB Stack-Up Design

Before designing multi-layer PCB circuit boards, designers need to confirm the circuit boards structure primarily based on the scale of circuit, the size of circuit boards, and the requirements of electromagnetic compatibility (EMC). It means that designers have to decide to use 2, 4, 6, or more layers of circuit boards. If the design requires the use of high density ball grid array (BGA) devices, the minimal number of wiring layers required for these devices must be considered. For years, people always believe that the less PCB layers, the lower the cost, however, there are many other factors affecting PCB manufacturing costs. In recent years, the differences between costs of multi-layer boards have been reduced significantly. As soon as the number of layers been determined, the placement of the inner layer and how to distribute different signals in these layers can then be decided --- this is the stack-up design of multi-layer PCB. Careful planning and choosing rational stack-up designs beforehand will save a lot of efforts in the following wiring and future production.

 

1.1 Layer Selection Principle

There are many factors to consider when determining the number of layers of multi-layer PCB board. For experienced designers, they will emphasize on the analysis of the bottlenecks of PCB wiring after the pre-placement of devices. In combination with other EDA tools to analyze wiring density of circuit board; and combined with the quantities and kinds of signal lines with specific wiring demands, such as differential lines, sensitive signal lines, to determine the number of signal layers; and then to determine the number of internal power layer according to the type of power supply, isolation and immunity requirements. Therefore, the layer number of the whole circuit board plates is basically determined.

The following table is the empirical data to determine number of signal layers based on the PIN density, for reference.

Ps: Definition of PIN density: Area of board (square inch)/ (Total number of pins on the Board/14)

 

1.2 PCB Stack-Up Principle

After the number of circuit board layers determined, the following job is to reasonably arrange the placement order of the circuit of each layer. In this part, there are two main factors to be considered:

(1) The distribution of special signal layers

(2) The distribution of power layer and ground layer

The more layers of circuit boards, the more varieties of arrangement of special signal layers, ground layers and power layers, thus it is more difficult to choose the best combination method, but the general principles are as follows.

(1) The signal layer should be next to an internal power layer (internal power/ground layer), shielded by the copper film of internal power layer.

(2) The internal power layer should be integrated with ground layer tightly, which means the thickness of medium between internal power layer and ground layer should take the smaller value, in order to improve the power supply capacitor between the internal power layer and ground layer, and increase the resonant frequency. If the electric potential difference between internal power layer and ground layer is not significant, a smaller insulation thickness can be used, like 5mil (0.127mm).

(3) To avoid the two signal layers directly adjacent. It is easy to introduce crosstalk between adjacent signal layers, leading to the fail of the circuit. To place a ground layer between two signal layers can avoid cross talk efficiently.

(4) Multiple grounded internal power layers can reduce the ground impedance effectively. For example, A signal layer and B signal layer use ground plane respectively can reduce common-mode interference effectively.

(5) The symmetry of layer structure.

 

1.3 Demonstration

For your reference, a stack-up design for the four, six, and eight layered high speed digital signal PCB is demonstrated in below:

1.3.1 Four Layer Stack–Up

Figure 1.3.1 Four Layer PCB Stack-Up Example

The high speed signals on the top layer are referenced to the ground plane on layer 2. Since the references for the high speed signals on the bottom layer are the power planes on layer 3, it is necessary to place stitching capacitors between the aforementioned power planes and ground. In this stack up, it is preferential to route high speed signals on the top layer as opposed to the bottom layer so that the signals have a direct reference to the ground layer. For some designs it may be desirable to have the bottom layer as primary high speed routing layer. In this case, the power and ground usage on Layer 2 and 3 could be swapped.

1.3.2 Six Layer Stack-Up

 

Figure 1.3.2 Six Layer PCB Stack-Up Example


In this example, the reference planes for the high speed signals on the top layer are the power planes on layer 2. Stitching capacitors from the associated reference power plane to ground are therefore required. The signal reference for the bottom layer is the ground plane on layer 5. In this stack-up, it is preferable to route high speed signals on the bottom layer. As in the previous example, power and ground layers could be swapped if it is desirable to have the primary high speed routing layer on the top layer.

The reference planes for signals on layer 3 are located on layer 2 and 5. The same reference planes are used by signals routed on layer 4. As the reference planes are on layers which have a relatively large distance from signal layers 3 and 4, the traces would need to be very wide in order to achieve a common impedance of 50Ω. Therefore, these layers are not suitable for routing high speed signals. In this stack-up approach, layers 3 and 4 can only be used for routing low speed signals where impedance matching is not required.

1.3.3 Eight Layer Stack-Up

Figure 1.3.3 Eight Layer PCB Stack-Up Example


The signals on the top layer are referenced to the plane in layer 2, while the signals on the bottom layer are referenced to layer 7. The reference planes for signal layer 3 are the ground plane on layer 2 and the power planes on layer 4. When routing high speed signals on layer 3, stitching capacitors need to be placed between the power and the ground planes. The power planes on layer 5 and 7 are used as references for the high speed signals routed on layer 6.

The inner layer 6 with the two adjacent ground planes is the best choice for routing high speed signals which have the most critical impedance control requirements. The inner layers cause less EMC problems as they are capsulated by the adjacent ground planes. As layer 3 is referenced to a power plane, outer layer 1 and 8 are preferable for high speed routing if layer 6 is already occupied.

em_strings

Embedded Systems

Posted by em_strings Aug 21, 2014

Hi ,

 

Embedded Strings inc  is a well-established company which specializes in the design, development, testing and manufacturing of complex embedded systems/Hardware. Our target markets are healthcare, telecommunication, aerospace and remote monitoring.


We have delivered customized hardware and software products that have application in wireless sensor networking, wireless tracking, digital signal processing and innovate medical monitoring devices.


We specialize in Field Programmable Gate Array design , we have developed our own VHDL/Verilog ip cores that have been integrated in high performance embedded systems, Nios SOC , ARM SOC and Digital Signal Processing.


We also have in-house resource to design multi-layer PCB using leading edge design tool Altium.


Please feel free to contact us in case you need to utilize any of the services that our company provides. We guarantee you complete security and confidentiality of information that you will share with us.

 

 

Thanking you ,


Ahmed Asim Ghouri

Embedded Strings inc

Website : www.emstrings.com

Email : support@emstrings.com

A Sensing node consists of methane gas sensor, carbon monoxide gas sensor, accelerometer sensor, temperature sensor and RS232 interface circuit with dual port RAM. Methane gas sensor and carbon monoxide gas sensors are placed on stationary node because its concentration is lighter than so it detects near the roof of the mine. The purpose of using accelerometer is to detect the earth quake type of activities. The Sensing node gets data from neighbouring Sensing node and sends its data to the next Sensing node.

 

The main computing microcontroller in this Hardware is CC430F6137. There are various gas sensors connected to Sensing node which will help monitor explosive and toxic gases within the mine environment. To monitor any structural change in the mine the Sensing node will analyze accelerometer data and to prevent any fire it will also monitor temperature inside the mine.

 

Block_dia.jpg

 

 

There are number of sensors connected to the microcontroller as shown in figure 5.The data of some of these sensors will be captured by built-in 12 bit ADC inside the CC430f6137.To extend the addressable memory an external SRAM has been connected via SPI interface whereas Accelerometer is connected via I2C bus.

 

Schematic Design

 

The complete schematic design of Sensing node comprises of 3 sheets which are connected with each other using off sheet connectors. The first sheet has a main computing unit of CC430 with CO sensor circuit, Methane gas sensor, Accelerometer and battery monitoring circuit. The second sheet has a RF matching circuit for CC430 RF Radio Core and the 3rd sheet has a power supply circuit for power-up all the modules.

 

 

Schematic_Sensing_node.jpg

schematic design of Sensing node. The gas sensor output is connected to the voltage clipping circuit because the A/D of CC430 can read maximum of 3.3V and gas sensors output varies from 0V-5V.The Output of clipping circuit is connected to CC430  via A/D convertor. The A/D reads the output of Methane and CO gas sensor and translates its voltage level to the respective gas concentration. The Accelerometer is connected to CC430 via I2C interface. The battery monitoring circuit output is connected to A/D of CC430. A/D read the value of voltage from battery monitoring circuit and displays the status of the battery on respective LED. A 1Kbit of SRAM is included to stationary node due to insufficient internal memory of CC430.

 

 

 

RF_matching_ckt.jpg

 

Following is the power supply circuit diagram supplying +3.3V and +5.0V

 

power_ckt.jpg

 

During testing we were able to send and receive data at a distance of 100 meters with RF power output of +12dbm

 

Embedded Strings inc  is a well-established company which specializes in the design, development, testing and manufacturing of complex embedded systems/Hardware. Our target markets are healthcare, telecommunication, aerospace and remote monitoring.


We have delivered customized hardware and software products that have application in wireless sensor networking, wireless tracking, digital signal processing and innovate medical monitoring devices.


We specialize in Field Programmable Gate Array design , we have developed our own VHDL/Verilog ip cores that have been integrated in high performance embedded systems, Nios SOC , ARM SOC and Digital Signal Processing.

Please feel free to contact us in case you need to utilize any of the services that our company provides. We guarantee you complete security and confidentiality of information that you will share with us.

 

 

Thanking you ,


Ahmed Asim Ghouri

Embedded Strings inc

Website : www.emstrings.com

Email : support@emstrings.com

skipbruce

PCB Panel Design

Posted by skipbruce Aug 18, 2014

1.5 Printed Cuicuit Board Panel Design

There are two problems to consider when design panel: one is how to place the boards; and the other is the way of connection.

1.5.1  Panel Layout

Panel can increase productivity and save on production costs; the first thing to consider in panel design is how to place small plates together to make a lager board. It is recommended that the basis of panel design is when the final size is close to the ideal size (Figure1.2.1).

1.5.1.1 PCB board’s long side length ≥ 125mm

When PCB board’s long side length ≥ 125mm, the boards can be placed as Figure 1.5.1.1 shows. The perfect number of boards is achieved when the final size is consistent with as (Figure1.2.1) requires. The stiffness of this placement is beneficial for the wave-soldering. Figure 1.5.1.1(a) is a typical panel, and Figure 1.5.1.1(b) is suitable for the situation that the rounded corners required after the separation of daughter boards.

(a) V-shaped groove separating method

 

(b) Slotted hole separating method

Figure 1.5.1.1 Panel

1.5.1.2 PCB Board’s long side length < 125mm
When PCB board’s long side length < 125mm, the boards can be placed as Figure 1.5.1.2 shows. The perfect number of boards is achieved when the final board length is consistent with as Figure1.2.1 requires. When this method is used, the rigidity of boards should be concerned. Figure 1.5.1.2 (a) is a typical V - shaped groove separated panel, there are three perpendicular craft edges to the PCB transfer direction with double-sided deposited copper foil, to enhance the stiffness. Figure 1.5.1.2 (b) is suitable for the situation that the rounded corners required after the separation of daughter boards, and the joint stiffness of separated sides paralleled to the PCB transfer direction should be concerned.

 


(a)V-shaped groove separating method


(b) The Long Slot plus a Small Circular Hole Separating Method

 

Figure 1.5.1.2 Panel

1.5.1.3 Panel of Sketch Plate

Pay attention to the connection between panel and panel, and try to keep each separated connection in a line, as 1.5.1.3 shows.

(a) L Shaped Panel

(b) T Shaped Panel

Figure 1.5.1.3 Panel of Sketch Plate

1.5.2 Connection of Panel

There are two main connection methods for panel: Double face carved V-shaped groove (V-CUT), and the long slot plus a small circular hole (commonly known as stamp hole), depending on the shape of the PCB.

1.5.2.1 V-CUT connection method

When it is straight-lined connection between plate and plate, the plate margin is neat and does not affect devices installation; the V-CUT method can be used. V-CUT is a through type, and cannot turn in the middle. Currently SMT Board is widely used, characterized with neat and level edges after separation and low processing costs, which is recommended as priority.

a) The two sides of V-CUT line (A side and B side) require a no device and no wire area that is not smaller than 1mm, to avoid the damage to devices and wires when separating.

b) After cutting the V-shaped groove, the remaining thickness X should be 1/4 to 1/3 of the board thickness Y, which is not smaller than 0.4mm. Board bears heavier can take upper limit, and vice versa. The misalignment of the upper and lower sides cut S of V-shaped groove must be less than 0.1mm.

The design requires being consistent with Figure 1.5.2.1.

Figure 1.5.2.1 Design Requirements of V-Cut

1.5.2.2 The Long Slot plus a Small Circular Hole Connection Method

The connection method of long slot plus a small circular hole, also known as stamp hole method, is suitable for any shapes of daughter boards. As the margin area is not neat and level after separation, it is not recommended for those PCB with fixed conduit ferrule.

Requirements for the long slot plus a small circular hole method: The width of long slot is usually between 1.6mm and 3.0mm, and the length is about 25mm to 80mm, the connection bridge between slot and slot is generally 5mm to 7mm, with several small circular holes placed, and the diameter Ф of these holes is 0.8mm ~1 mm, the distance from the center of the aperture to the outside is 0.4mm – 0.5mm: Thicker boards take smaller value and thinner boards take larger value, it is a typical value in Figure 1.5.2.2. The length of the cutting groove is based on the PCB routing directions, assembly process, and the size of PCB. The smaller the aperture, the neater the margin area.

Figure 1.5.2.2 The Long Slot plus a Small Circular Hole Method

1.5.2.3 The Design of Connection Bridge

When design connection bridge, it is mainly to consider: whether the margin area after separation is neat or not; whether it is convenient to separate or not; is the stiffness enough for production; the material, thickness and total weight of single plate; the distance between connection bridges (the recommended distance is 60mm). In order to make the margin area neat after separation, the separating holes are usually placed on the sidelines or slightly within the daughter board.

In PCB (Printed Circuit Board) design, it is best not to exceed the batch-production technology level of manufacturers. Otherwise, the PCBs may not be able to be processed, or have high associated costs.

1.1 Range of Dimensions

The ideal dimensions for production are as follows: width (200mm-250mm), length (250mm-350mm). For a PCB with length shorter than 125mm or width shorter than 100mm the panelization method can be used to transform the dimensions of the PCB to ideal values according to requirements of production. This facilitates component insertion and soldering.

1.2 Shape

a) The shape of the PCB is rectangular. If a PCB does not need a panel, the four corners of the plate must be rounded as shown in Figure 1.2.1. If a panel is needed, the four corners of the PCB must be rounded after being panelized, with radius 1mm-2mm.

Schematic Diagram of PCB Shape

Figure 1.2.1 Schematic Diagram of PCB Shape

To ensure stability in the transmission process, the penalization method is used to transform irregularly shaped PCBs. Specifically, the gap on the corner must be supplemented, as shown in Figure 1.2.2. Otherwise, special tooling design is needed.

Schematic Diagram of Technological Panelization

Figure 1.2.2 Schematic Diagram of Technological Panelization

b) To ensure that the PCB is stably transferred by chains, any gap on a pure SMT must have length shorter than 1/3 of the corresponding edge, as show in Figure 1.2.3.

 

Permitted Size of Gap

Figure 1.2.3 Permitted Size of Gap

c) Figure 1.2.4 shows design requirements for gold fingers: chamfers are designed on the insertion edge as required; (1-1.5) x 45o chamfers or (R1-R1.5) circular beads should be designed on the two sides of the insertion board to facilitate insertion.

Design of Chamfer of Gold Fingers

Figure 1.2.4 Design of Chamfer of Gold Fingers

 

1.3 Technology Edge

For a PCB without a technology edge, scopes that are 5mm or further than 5mm from the positive or negative edges of the board cannot have any components or soldering spots; and the wiring position must be at least 3mm from edges of the board. If short-insertion wave soldering is adopted, the board must meet the width requirements of general transfer edges, and the height of components 10 mm from board edges must be limited to 40 mm (containing the thickness of the board), in consideration of the characteristics of short-insertion wave braziers, as shown in Figure 1.3.1.

 

Schematic Diagram of PCB Transfer Edge

Figure 1.3.1 Schematic Diagram of PCB Transfer Edge

If the size of the keep-out area on the transfer edge of the PCB board cannot meet above-stated requirements, a 5mm or wider processed edge must be added to the corresponding board edge. The smoothing radius of the processed edge is 2mm, as shown in Figure 1.3.2.

Design Requirement 1 of PCB Technology Edge

Figure 1.3.2 Design Requirement 1 of PCB Technology Edge

To meet the special requirements of structural design, if a component protrudes from the transfer edge of the PCB, the width of the auxiliary edge must meet the requirements shown in Figure 1.3.3.

Design Requirement 2 of PCB Technology Edge

Figure 1.3.3 Design Requirement 2 of PCB Technology Edge

1.4 Fiducial Mark

Fiducial marks are needed for the placement of equipment adopting optical locations. They are used for overall automatic location of chip mounters, and must have high contrast ratios when illuminated by a chip mounter.

1.4.1 Design of Fiducial Marks

Requirements of appearance design of fiducial marks are as follows:

1. Solid circle;

2. Inner diameter = 1mm;

3. Ring-shaped radius of the solder mask is 0.5mm, as shown in Figure 1.4.1.

Schematic Diagram of Fiducial Mark

Figure 1.4.1 Schematic Diagram of Fiducial Mark

1.4.2 Application of Fiducial Marks

Fiducial marks are mainly applied to panel, plate and local positions, as shown in Figure 1.4.2.

Application of Fiducial Mark

Figure 1.4.2 Application of Fiducial Marks

1.4.2.1 Global Fiducials

Three fiducials must be selected from the four corners of the board. If both the surfaces of the board have placement components, each surface must have fiducial mark, as shown in Figure 1.4.3.

Location of Fiducial Mark on the Plate

Figure 1.4.3 Location of Fiducial Mark on the Plate

1.4.2.2 Panel Fiducials

Global fiducial marks of three panels are required. The diagonal point of each panel should have at least two fiducial marks. In special situations, you must negotiate with technologists to determine whether the two fiducial marks on two panels can be omitted or not. However, the global fiducial marks of the panels must be reserved.

1.4.2.3 Local Fiducials

The lead pin pitch is smaller than 0.4mm. For QFP packaging chips with more than 144 lead pins, two marks at opposite corners of the chip need to be increased. If the above-stated components are close (with distances smaller than 100mm), they can be regarded as a whole, and two local fiducials need to be increased on the diagonal position, as shown in Figure 1.4.4.

Local Position of Fiducial Marks

Figure 1.4.4 Local Position of Fiducial Marks

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