In Storage Insights #5, we provided a guide to the Embedded Mulitmedia Card (eMMC), with technical details, operation information, and various commands. In Storage Insights #6 we will dive deeper into SATA (Serial ATA), discussing layering and compatibility.
Serial ATA was introduced in 2003. It evolved from Parallel ATA (PATA), and shortly after its introduction replaced PATA in PCs and other systems.
SATA SSD has several advantages over PATA hard drives developed in the 1980s. SATA cables are thinner, more flexible and smaller than the ribbon cables required for conventional PATA hard drives.
Setting SATA Controller Modes
Serial ATA hard drives connect to a computer’s motherboard via SATA Controller hardware that manages the flow of data. Putting SATA in IDE mode means the hard drive is recognized as a PATA device — a situation that provides better compatibility with older hardware but comes with the tradeoff of lower performance.
Setting a SATA controller to Advanced Host Controller Interface (AHCI) offers higher performance than IDE mode and enables features such as Hot Swapping on SATA drives. The redundant array of independent disk (RAID) mode supports both AHCI functions and RAID data protection features.
SATA Functional Description
The SATA specification defines three distinct protocol layers: physical, link, and transport.
The physical layer defines SATA’s electrical and physical characteristics (such as cable dimensions and driver voltage level and receiver operating range), as well as the physical coding subsystem (bit-level encoding, device detection on the wire, and link initialization).
Physical transmission uses differential signaling. The SATA PHY contains a transmit pair and receive pair. When the SATA-link is not in use, the transmitter allows the transmit pins to float to their common-mode voltage level. When the SATA-link is either active or in the link-initialization phase, the transmitter drives the transmit pins at the specified differential voltage (1.5V in SATA/I).
SATA physical coding uses a line encoding system known as 8b/10b. This scheme serves multiple functions required to sustain a differential serial link. First, the stream contains necessary synchronization information that allows the SATA host/drive to extract the clock. Note the SATA link has no clock line. The 8b/10b encoded sequence embeds periodic edge transitions to allow the receiver to achieve bit-alignment without the use of a separately transmitted reference clock waveform. The sequence also maintains a neutral bitstream, which let’s transmit drivers and receiver inputs be AC Coupled. Generally, the actual SATA signaling is half-duplex, meaning that it can only read or write data at any one time, although Full Duplex operation is physically present.
Also, SATA uses some of the special characters defined in 8b/10b. The PHY layer uses the comma character to maintain symbol-alignment. A specific four-symbol sequence, the ALIGN primitive, is used for clock rate-matching between the two devices on the link. Other special symbols communicate flow control information produced and consumed in the higher layers (link and transport).
Separate point-to-point AC-coupled (LVDS) links are used for physical transmission between host and drive.
The Physical layer is responsible for detecting the other SATA/device on a cable, and link initialization. During the link-initialization process, the PHY is responsible for locally generating special out-of-band signals by switching the transmitter between electrical-idle and specific 10b-characters in a defined pattern, negotiating a mutually supported signaling rate (1.5, 3.0, or 6.0 Gbit/s), and finally synchronizing to the far-end device’s PHY-layer data stream. During this time, no data is sent from the link-layer.
Once link-initialization has completed, the link-layer takes over data-transmission, with the PHY providing only the 8b/10b conversion before bit transmission.
After the PHY-layer has established a link, the link layer is responsible for transmission and reception of Frame Information Structures (FIS) over the SATA link. FIS are packets containing control information or payload data. Each packet contains a header (identifying its type), and payload whose contents are dependent on the type. The link layer also manages flow control over the link.
Layer number three in the serial ATA specification is the transport layer. This layer has the responsibility of acting on the frames and transmitting/receiving the frames in an appropriate sequence. The transport layer handles the assembly and disassembly of FIS structures, which includes, for example, extracting content from register FISs into the task-file and informing the command layer. In an abstract fashion, the transport layer is responsible for creating and encoding FIS structures requested by the command layer, and removing those structures when the frames are received.
When DMA data is to be transmitted and is received from the higher command layer, the transport layer appends the FIS control header to the payload, and informs the link layer to prepare for transmission. The same procedure is performed when data is received, but in reverse order. The link layer signals to the transport layer that there is incoming data available. Once the data is processed by the link layer, the transport layer inspects the FIS header and removes it before forwarding the data to the command layer. In the end, what is left parallels the PATA type register based information.
The designers of SATA standard as an overall goal aimed for backward and forward compatibility with future revisions of the SATA standard. To prevent interoperability problems that could occur when next generation SATA drives are installed on motherboards with standard legacy SATA 1.5 Gbit/s host controllers, many manufacturers have made it easy to switch those newer drives to the previous standard’s mode.
SATA Standards and Revisions
The technical specifications governing Serial ATA device interfaces are authored by the nonprofit SATA-IO industry consortium. The consortium has made several revisions to SATA standards to reflect increased data transfer speeds.
- SATA Revision 1.0 devices were widely used in personal desktop and office computers, configured from PATA drives joined together in a master/slave configuration. SATA Revision 1 devices topped out at a transfer rate of 1.5 Gb/s or 187.5 MB/s.
- SATA Revision 2.0 devices doubled the transfer speed to 3.2 Gb/s or 400MB/s with the inclusion of port multipliers, port selectors and improved queuing.
- SATA Revision 3.0 interfaces support drive transfer rates up to 6 Gb/s. SATA Revision 3 drives are back compatible with SATA Revision 1.0 and SATA Revision 2.0 devices, albeit with a lower transfer speed.
- SATA Revision 3.1 is an intermediate revision that added final design requirements for SATA Universal Storage Module for consumer-based portable storage applications.
- SATA Revision 3.2 added a specification known as SATA Express (SATAe), which supports simultaneous use of SATA ports and PCI Express (PCIe) lanes.
- SATA Revision 3.4 Durable /Ordered Write Notification: enables writing selected critical cache data to the media, minimizing impact on normal operations.
SATA Design Specs for Flash Storage
In 2009, the SATA-IO consortium unveiled the mSATA for small form solid-state drives SSDs. The M originally stood for mini, but that designation is no longer made and the specification is referred to as mSATA. An mSATA device is a Flash drive that conforms to the SATA-IO protocol specification and is mainly used in laptops, and other portable computing devices. The mSATA specification maps Serial ATA signals to an internally mounted PCIe card in a computer’s motherboard.
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Excerpts from the original Delkin document: