MIT assistant professor, Max Shulaker’s presentation at DARPA’s Electronics Resurgence Initiative Summit was welcomed by a round of applause when he showcased a silicon wafer that can compete with the world’s state-of-the-art foundries. The wafer is just the beginning towards DARPA’s plan to turn a state-of-the-art foundry into something that can create chips.
MIT assistant professor Max Shulaker presents the 3D carbon nanotube IC at the DARPA Electronics Resurgence Initiative Summit. (Image Credit: DARPA via ieee)
“This wafer was made just last Friday… and it’s the first monolithic 3D IC ever fabricated within a foundry,” he announced to the audience of several hundred engineers in Detroit. The wafer included several chips made of a layer of CMOS carbon nanotube transistors along with a layer of RRAM memory cells assembled on top of each other and connected vertically together with a dense batch of connectors known as vias. The purpose of the project, titled 3DSoC, is to provide chips made of multiple layers with a 50-fold performance boost over traditional 7-nanometer chips used today. It’s an impressive goal to meet especially because the lithographic process the newer chips are built on (90-nanometer node) was used as state-of-the-art back in 2004.
3DSoC has been ongoing for a year now, but when the project reaches its 3.5 year goal, DARPA hopes to have a foundry technology that can produce chips containing 50-million logic gates, 4 gigabytes of nonvolatile memory, and 9 million interconnects per square millimeter between layers that can send and receive 50 terabits per second while using up less than 2 picojoules per bit.
Doing all of that isn’t possible just yet, but it is a milestone they hope to reach as the project progresses. The project is a collaborative effort with SkyWater Technology Foundry and other partners “we’ve completely reinvented how we manufacture this technology, transforming it from a technology that only worked in our academic labs to a technology that can and is already today working inside a commercial fabrication facility within a U.S. foundry,” he said.
An advantage of using this technology over the 2-D silicon used today is the ability to stack layers of CMOS logic and nonvolatile memory while connecting the layers with vertical connections which are narrower and more heavily packed than any other 3-D technology that may exist. However, this type of technology can’t be implemented in silicon because the temperatures that are required to build a layer of silicon logic, about 1,000 degrees Celsius, can cause destruction to the layer beneath it. The technology involved in the 3DSoC project uses carbon nanotube based transistors, which can be assembled at temperatures as low as -450C. The RRAM tiers can also be constructed at a low temperature, as well, making it possible for multiple layers to be assembled without damaging any tiers beneath the layer.
The next milestone for the project is to combine two layers of nanotube transistors RRAM at the end of the year. Afterwards, SkyWater and the rest of the team will be working on making improvements to the yield. “We’re achieving economically viable bit yield [for RRAM] at this point,” Brad Ferguson, CTO of SkyWater says. “For the first run, that’s pretty darn good.”
In the concluding phase, potential customers and partners will be using the process design kit in order to produce prototype chips. From that point onwards, SkyWater will then start a business around the process and will make the technology available to other foundries via licensing.
What’s even more exciting is performance boost could continue to grow. The entire process could be improved upon to work at 65 nanometers or more advanced manufacturing nodes, making room for higher densities and quicker, powerful systems. “Once 3D SoC is implemented at the relaxed mature 90-nm node, we have decades-worth of [innovation] to be had relying on conventional techniques,” said Shulaker.
That would also set SkyWater apart from other leading foundry companies. “It perhaps makes us relevant to customers that need the bleeding edge, like Qualcomm,” said Ferguson, referring to statements made earlier that day by Qualcomm CEO Steve Mollenkopf. “They say they have to be at the leading edge. Now we, [a 90-nanometer foundry], could potentially be relevant to them.”
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