Applied Materials’ new solution involves combining seven process technologies in one system under a high vacuum. This improves chip performance and power consumption. (Image Credit: Applied Material)

 

Recently, Applied Materials announced it achieved a chip wiring breakthrough, allowing logic chips to be scaled down to 3nm and beyond. As a result, the width between circuits is three billionths of a meter. Existing chip factories produce 7nm and 5nm chips, which means that these 3nm chips represent the next generation of technology. Factories that cost over $22 billion are expected to produce these 3nm chips.

 

Chip manufacturers can still use the same wiring technology in their factories to produce these chips. Switching from 5nm to 3nm helps with the semiconductor chip shortage that impacted the electronics industry. However, it won’t be in production immediately. There are transistor-related, interconnect scaling and patterning issues (extreme ultraviolet and multi-patterning) that need to be solved first.

 

Although size-reduction greatly improves transistor performance, interconnect wiring doesn’t benefit from this. Smaller wires generate more electrical resistance, resulting in performance loss and more power consumption. If a breakthrough wasn’t achieved, interconnect through resistance increases by a factor of ten from the 7nm to 3nm node, which offsets the transistor scaling benefits. 

 

Applied Materials’ newly-developed materials engineering solution, called the Endura Copper Barrier Seed IMS, combines seven process technologies in a system under a high vacuum. That includes ALD, PVD, CVD, copper reflow, surface treatment, interface engineering, and metrology. By combining these processes, conformal ALD gets replaced with selective ALD, removing a high-resistivity barrier at the interface.

 

Copper reflow technology, which enables void-free gap fill in narrow features, is also used in the solution. This reduces electrical resistance at the contact interface by 50%, boosting chip performance, power consumption and enabling logic scaling to progress to 3nm and beyond. Electrical flow in a chip is improved while allowing it to operate at the next miniaturization level.

 

“A smartphone chip has tens of billions of copper interconnects, and wiring already consumes a third of the chip’s power,” said Prabu Raja, Senior Vice President and General Manager of the Semiconductor Products Group at Applied Materials. “Integrating multiple process technologies in vacuum allows us to reengineer materials and structures so that consumers can have more capable devices and longer battery life. This unique, integrated solution is designed to accelerate the performance, power, and area-cost roadmaps of our customers.”Now, worldwide leading foundry-logic customers are utilizing the Endura Copper Barrier Seed.

 

 

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