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FPGA Group

82 posts
Have you ever wanted to integrate a Microchip PHY into the Xilinx Ecosystem, but previously had no proven reference designs available to mitigate risk factors? Recently Avnet released the Network FMC (http://avnet.me/fmc-network1 ), which is a dual Microchip Ethernet 10/100/1000 PHY Low Pin Count (LPC) FMC expansion module. I will take you through the design choices made in the development of the Network FMC expansion module and various lessons learned during this development process.   &# ...
Instantiating LUT6 Primitives Part 2  Today I will show a couple of examples where LUT6 primitive instantiations make sense. To keep things short and simple these are somewhat artificial examples but situations like these tend to show up all the time in hardware designs. Let's say we need a 48-input AND function. This can be coded very easily behaviorally, especially if we take advantage of the new VHDL-2008 features:   library IEEE; use IEEE.STD_LOGIC_1164.all;  entity WideAN ...
Instantiating LUT6 Primitives  In the previous post we have already seen how to instantiate FPGA primitives, SRL16s in that case. The role of the synthesis tool is to take HDL behavioral code and translate it into a netlist of FPGA fundamental building blocks called primitives. This is very much like the software design flow, where a C compiler takes C code and produces machine code that a processor can execute. The same way a C compiler lets you embed assembly code into your C program, th ...
The Universal DELAY Building Block Part 2, the one with the cake  In the last post I have introduced an example of a universal delay block that uses a behavioral implementation to create a reusable module that can be used to delay a signal by an arbitrary but fixed value. Both the delay size and its width are generic respectively unconstrained, which makes the design reusable. While the behavioral implementation is quite compact and elegant, the synthesis result is not always what we reall ...
The Universal DELAY Building Block  This is the first post in this blog in which I will try to actually design something useful based on the ideas introduced so far. Also, instead of just short code snippets, the code examples in this post are complete and they can be simulated, synthesized and used in actual designs.   We will try to create a generic and reusable delay module - the goal is to delay a signal of some given type by a fixed but arbitrary number of clocks, this is a fund ...
We're Not in Kansas Anymore  In this post we will try to do things you probably never tried to do using VHDL, assuming they were not even possible in such a low level language.   VHDL and Verilog/SystemVerilog are considered low level hardware design languages, compared with C/C++ based HLS flows for example. Only schematic capture is lower on the totem pole and hopefully nobody is still doing FPGA designs using schematics anymore. But the low level label attached to HDLs is only pa ...
VHDL User Defined TypesNUMERIC_STD SIGNED is not a good choice for fixed point arithmetic  Most signal processing applications require handling fixed point data types, not just integers. These numbers have a binary point, assuming we use binary or base 2 representation, with an integer part to the left of the binary point and a fractional part to the right of it. While it is possible to use integer numbers for that with an implicit binary point position there are numerous problems when try ...
Beyond STD_LOGIC  In the last post we just started to scratch the surface of VHDL types. This time we will try to go deeper - which types should we use, what are their properties and limitations, what are the main pitfalls a beginner would encounter and how to solve them.   We have seen that while the basic type for software programming is INTEGER, of various but fixed sizes, signed or unsigned, the VHDL fundamental type is the 1-bit STD_LOGIC. It has 9 possible values, some of which ...
What's Your Type?  People new to VHDL usually come from a software background, maybe C/C++ or Java and might have a difficult time grasping the fundamental concepts of HDLs. VHDL in particular can be used as a sequential software language - everything you can do in C you can do in VHDL and while this might make sense when creating testbenches for functional simulation it is not the right approach for actual hardware design.   The first fundamental concept you have to grasp as a VHDL ...
Note: The v1.0 Ultra96 board definition files (BDF) embedded in Vivado 2018.1 and 2018.2 have a bug. The latest BDF is on the Avnet GitHub here: https://github.com/Avnet/bdf . The article below describes the parameters included in the v1.2 board definition file.   The Avnet Ultra96 board from Avnet has 2 GB of LPDDR4 RAM that is interfaced to the Zynq UltraScale+ MPSoC's Processing System (PS) DDR Controller. This versatile controller is described in Chapter 17 of the ZU+ Technical Referen ...
Two Free VHDL Books  If you installed Vivado WebPACK, the free version of Xilinx FPGA design tools, you are ready now to start creating your first hardware design. There are at least three different ways to program a Xilinx FPGA today, using a hardware description language like VHDL or Verilog/SystemVerilog, using Vivado HLS using C/C++ and Vivado SystemGenerator or ModelComposer which requires Matlab and Simulink. Each design flow has advantages and disadvantages and the third one is not ...
Why learn FPGA Design?  I have been asked in the comments why invest time and money to learn how to use FPGAs? First of all, if you are interested in advanced digital hardware design FPGAs are essentially the only game in town. Unless you are working on million dollar ASIC designs, the only way to do really advanced hardware design at a reasonable cost is with an FPGA.   Yes, there are DSPs and embedded micro-controllers and if you want to just toggle an LED a few times a second then ...
Hello all,   I wanted to create a post letting everyone know about a new white paper that was generated by one of my colleagues, I have linked it below.  In this white paper, he goes through and describes a design flow that would allow primarily a software engineer to easily work with an FPGA solution that leverages Open-Source C code to produce a Fast Fourier Transform (FFT).  Utilizing the Avnet SOM strategy would allow someone that is not as hardware oriented to be able to pro ...
Running Out of Excuses  Can you do FPGA design or teach yourself the skills required to do that with a $0 budget? Electrical engineers (and hobbyists and students and young - or old for that matter - people interested in electronics) are running out of excuses for not trying to learn FPGA design. In the past we heard that the FPGA software tools are expensive, they cost thousands of dollars, FPGA evaluation boards were an arm and a leg and you needed very expensive lab equipment like osci ...
fpgaguru

The Art of FPGA Design

Posted by fpgaguru Jul 10, 2018
Hi,   This is a new blog on the Art of FPGA Design. For those who want to follow along, I will try to add a new post every week.   While intended mainly for beginners initially, this is not an FPGA 101 kind of material. There are many of them that can be found online, including some excellent ones here on the Element 14 site. Some familiarity with FPGAs, HDLs and hardware design in general will be assumed. Some software programming experience might help (or hinder, we will have to se ...

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