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FPGA Group

219 posts
The goal of this blog series is to master the Xilinx Zynq. I'm using the PWM design of my previous posts, and now switch to the raw AXI memory map interface between ARM and FPGA. In the previous post, I used AXI GPIO, the first step to memory mapped interface between the Linux and FPGA parts. Now I'm using the pure memory map (MMIO).   There isn't a lot of difference between the previous blog and this one. In fact, the previous one was a little but easier to use. But this one is our st ...
I posted a series of FPGA blogs. They focus on the toolchains and steps to get a working design. A common theme in those articles is the VHDL source. Each time, it's a PWM generator. A specific kind of PWM block: it can generate complementary output signals, to drive a transistor half bridge.   In this post, I'm drilling into that VHDL part.     Why this PWM module with 2 outputs and dead time I wanted to use a relevant exercise that solves a common task in electronics: driv ...
The goal of this blog series is to master the Xilinx Zynq. I'm using the PWM design of my previous post and switch to AXI memory map interface between ARM and FPGA. I learned this from beacon_dave 's PYNQ-Z2 Workshop - AXI GPIO post.   ARM/Linux to FPGA interface: from GPIO to AXI memory mapped register  in the previous post, I made a PWM generator in VHDL for the Zynq. I used the ARM EMIO GPIO bus as the interface between ARM and FPGA fabric. This is a 64 bit bus. I used 8 bits ...
The goal of this blog series is to master the Xilinx Zynq. I'll try to build a PWM controller for a half bridge power design. I've made a PWM with dead time design for the Xilinx Spartan 6 FPGA in 2017. I'm now learning to design for Zynq (I got a Pynq-Z2 board from our balearicdynamics!). I use the 2017 Spartan 6 design as a starting point.     Goals for this post  I want to have that PWM VHDL design running on the Zynq, and be able to change the dead time and duty cycle fro ...
Instructions on how to add the Pynq-Z2 board to Vivado. This allows you to create projects and custom FPGA bit streams for it.   image source: customer action video after completing the instruction video of Cathal McCabe listed at the end of this post.   In the Vivado project creation wizard, there is a possibility to prime your design from a board definition. You don't need to find out what the exact FPGA is, and what hardware is available. There are more project preparation to ...
When in Doubt, Check the Devicetree  It recently came to our attention that the SATA interface was broken in Linux for the UltraZed-EV and UltraZed-EG.  This is one of those "Wait! What? I know this worked before!" sorts of issues.  After doing some sleuthing by going back and booting OS images from older BSPs on the UltraZed-EV I confirmed that, sure enough, SATA was working in Linux up through the PetaLinux 2019.2 BSP.  Something broke after that.  Perhaps related to ...
A bit about me The hardware Kit overview Accessories KV260 SoM and carrier board SoM versions Starter Kit versions Getting started More about the smartcam and other apps Not just petalinux PYNQ Ubuntu Using the KV260 with Vivado and Vitis 2020.2.2 Conclusion A bit about me I thought I'd start this with a little background about me. This is not, as you might suspect, because I like talking about myself. I think it's good to give a bit of cont ...
Multichannel Symmetric FIRs   In the last two posts we have considered the case when the FPGA clock frequency is faster than the FIR sample rate. The ratio between the system clock and the data sample rate is called the overclocking factor M. We have seen that there are two ways to take advantage of this, either implement M identical FIR channels with K DSP48s, where the filter order N is K for non-symmetric FIRs, 2*K for even-symmetric ones and 2*K-1 for the odd-symmetric case, or implem ...
I previously wrote about Board Definitions in this blog: How to Leverage Board Presets to Accelerate Your Vivado Design   That blog discussed creating your own Board Repo to add Board Definitions. Vivado has a built-in way to do this graphically, pulling the Board Definitions from a resource called the Xilinx Board Store. The purpose of this blog is to show an alternative way to add Board Definitions to Vivado. It is not intended that you do them both, so pick which method you prefer!  ...
This past week I took a look at the KV260 Vision AI Starter Kit courtesy of Xilinx and rscasny   https://www.xilinx.com/products/som/kria/kv260-vision-starter-kit.html   First thing first. This is Xilinx entry into the System on Module (SOM) market. The KV260 is a carrier board targeting AI vision applications. The kit carries a non-production version of the Kria SOM. Non-production meaning reduced operating temperature range. It's mainly targeted at software developers that can l ...
This is an update to the popular Avnet HDL git HOWTO (Vivado 2020.1 and earlier) blog post.   You may know that Avnet provides PetaLinux BSPs and other reference designs for the Xilinx Zynq and Zynq UltraScale+ Zed SOMs (MicroZed, PicoZed, and UltraZed) and development boards (MiniZed and Ultra96), but did you also know that Avnet provides Xilinx Vivado TCL and Linux bash scripts for users to build these designs?  Avnet provides git repositories on github for everything that is needed ...
This is an update to the popular Using Avnet Build Scripts to Build a PetaLinux BSP (2019.2 and earlier) blog post.   Like the Avnet HDL github repository of build scripts, IP, etc. for building the Vivado projects that are the hardware foundation for customers to use and customize, Avnet's PetaLinux github repository is also full of build scripts, bitbake recipes, etc. for creating BSPs that customers are able to use as the basis for their own Linux development on Avnet Zynq and Zynq Ultr ...
Hacking the Devicetree to Achieve the Linux QSPI Boot Trifecta This is a tale of pain, grief, and redemption when working through strange Linux behavior and boot failures, and what happens when the devicetree doesn't match the underlying hardware.   I recently programmed my QSPI with a new Linux OS image and now it won't reboot.  It booted the first time from QSPI, but now won't reboot.  Say what?  How can that be?   First, let's take a short trip in the PetaLinux BSP ...
Multichannel  and Overclocking FIRs - The Single Rate Symmetric Case   In the last post I created an overclocked or semi-parallel implementation of a systolic, non-symmetric FIR, where each DSP48 in the chain implements M taps of the filter. The filter sample rate is M times slower than the system clock rate, but the device utilization is also M times smaller, N/M DSP48s instead of the normal N, where N is the filter order.   Many times the FIR filter is symmetric and the DSP4 ...
Interested in implemented AI at the edge with the Avnet platforms ?   Check out my new designs for Vitis-AI 1.3, the latest edge AI solution for Xilinx based platforms.   Vitis-AI 1.3 flow for Avnet Vitis platforms This project provides detailed instructions for targeting the Xilinx Vitis-AI 1.3 flow to the following Avnet Vitis 2020.2 platforms: Ultra96-V2 Development Board UltraZed-EV SOM (7EV) + FMC Carrier Card UltraZed-EG SOM (3EG) + IO Carrier Card     Vitis-AI ...

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