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FPGA Group

105 posts
Continuing from where I left off in Driving a Laptop LCD using an FPGA, I moved the 'TMDS to LVDS converter board' to perf board, and soldered the differential pairs from the LCD panel onto it. I used headers (to connect wires) for the connections between the converter board and FPGA's PMOD ports, but not that I think about it, it might have been better to solder the headers so that it could be plugged directly to a PMOD (or 2 PMODs) without using wires. This setup was more stable, since the ...
In Path to Programmable Blog 7 - Trying out a PL-only VGA design & Path to Programmable Blog 10 - MiniZed does DVI/HDMI, I used the MiniZed that was sent to the Path to Programmable challengers to generate VGA & DVI/HDMI video.   Continuing with video related FPGA projects, I decided to attempt two more: Use the FPGA to drive a LCD panel that I salvaged from an old laptop Implement a HDMI sink on the FPGA, and send the incoming video the LCD panel.   This blog post covers t ...
Disclaimer: I posted this project hoping that it would be interesting and useful.  However, it is provided "as is" with NO WARRANTY of any kind and if you connect it to an actual organ you must know what you're doing to avoid damage to the organ or to the tuner.  The user assumes all risk using this project with actual hardware.   As electronics gets smaller and higher density it becomes more difficult and often impossible to repair and/or modify electronic products.  In too ...
Here is the new release 0.1 of XXICC.  I was very busy with work and family obligations over the last few years so I wasn't able to keep up with XXICC as I would have liked.  0.1 is a major release since it adds n-bit integers (1-32 bits) to GalaxC and GCHD.  These changes touched a lot of code and documentation.  I've tested what I could, but with this many changes there are bound to be some undetected bugs.  Please report any you find in the comments below, especially ...
Those of you with long memories will remember the first blog about this board: Ultra cheap and Tiny FPGA Board   I've built up a couple of boards and got them running some very simple start up software and VHDL. The good news is that there are only two small bugs on the board, neither is too grim to fix.   Other E14 members (notably jancumps ) have been Roadtesting the MAX32660 which provides one half of the good stuff on this board. My approach to coding the processor is very dif ...
This is a continuation of my on going N64 HDMI project. The last post can be found here: The N64=>HDMI Conversion Project: Part 2   I apologize for the delay in my updates. I am a full time college student and my studies always come first. I hope to get some work on my project done over the winter break.   I do have some updates however!   Since my last post I have done research on the ins and outs of analog TV signals. This lead me to the conclusion that my analysis prior t ...
The DSP48 Primitive - Instantiating the DSP48  Behavioral inference has many advantages - relatively simple and compact code, works with signed and unsigned operands of any size, hides the intricacies of the DSP48 primitive from the user. It should definitely be the first choice when coding a DSP based design if it produces the desired results in terms of device utilization and clock speed.   That's a big if, when things do not go as you want there isn't much you can do - fighting wi ...
The DSP48 Primitive - Behavioral Symmetric FIR Inference  The DSP48 primitive has an optional preadder function, which can be used to compute things like PCOUT=PCIN+(A+D)*B, which when used for implementing symmetric or anti-symmetric FIRs can reduce the number of multipliers used in half.   The following diagram shows how such a symmetric FIR is built using the case N=4, a symmetric FIR with 8 taps as an example: The forward data delay line is identical to the one for the non-sym ...
The DSP48 Primitive - Behavioral FIR Inference  As mentioned earlier, the DSP48 primitive is an essential part of any signal processing FPGA design and in over 90% of cases it's either FIR like sums of products or complex multiplications. For this reason we will focus now on efficient implementation of Finite Impulse Response filters with DSP48s, which will also cover other cases where computation of sums of products is required like linear algebra matrix multiplication and convolutional n ...
The DSP48 Primitive  This post will start a longer series dedicated to the DSP48 primitive, a MAC (multiply/accumulate) block which is the workhorse for any kind of signal processing design that requires lots of mathematical operations beyond simple additions or subtractions, which are well handled with fabric based implementations that use the dedicated carry chain primitives.   The DSP48, of which there are multiple flavors, one for each Xilinx FPGA family, started as a signed 18x1 ...
Using the Carry-Save Adder, The Constant Coefficient Multiplier  Multiplications in Xilinx FPGAs are done using DSP48s, which are primitives that consist of a 25x18 signed multiplier, a 25-bit preadder and a 48-bit postadder/accumulator. In UltraScale/UltraScale+ FPGA families the signed multiplier is 27x18 and the post adder has three inputs instead of just two. Depending on the FPGA size and family there are hundreds to thousands of such DSP48 primitives, that are able to do one multiply ...
Using the Carry-Save Adder, A Generic Adder Tree  In this post I will show how to implement an efficient and generic adder tree, we need to compute the sum of N elements, where N can be any value. The numbers we add are also arbitrary precision fixed point values, all the same range but otherwise unconstrained.   We can represent the input data as an unconstrained array of unconstrained SFIXED, which requires VHDL-2008 support - with Vivado we can synthesize and implement this but we ...
Using the Carry-Save Adder, Computing a Running Average  I will show in the next few posts some design examples where using a 3-input carry-save adder instead of the normal 2-input ripple-carry adder makes a significant difference. The first example is a running average, where we have a stream of input samples and we want to compute a continuous running average every clock, as the average of the last N samples. In mathematical terms:   y(n)=1/N*Sum(x(n-k)), k=0..N-1   As a firs ...
This is  a little test board I'm putting together to experiment with the MAX32660 processor and the Lattice UP5K Ultra Plus FPGA.   The UP5K is a tiny FPGA, available in a hand solderable 48 pin, 0.5mm pitch QFN with 5k LUTs, 15k bytes of embedded block RAM and 128k bytes of SPRAM (slowish ram in 32k byte blocks). It has 8 multipliers (16 x 16) and draws a static current of 75uA. They cost pocket money, about £5 a few at a time.   It's a volatile FPGA so it needs something ...
The Carry-Save Adder, two for the price of one  This post is about buying two adders but paying only for one of them.   When developing software the CPU and memory your code is running on is already paid for and there is little incentive to optimize your code to make it either smaller or faster. But as a hardware designer you literally pay for every LUT and FF in the FPGA you are using. If you could make your design smaller and faster you could do more with the same FPGA or you could ...

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