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2015
Release 0.0q has been replaced by: XXICC (21st Century Co-design) release 0.0r   Here is the new release 0.0q of XXICC.  0.0q adds logic capacity to Flavia implementation and allows you to specify pull-up, pull-down, and keeper circuits for FPGA I/Os in all implementations.  The Flavia architecture is now more consistent across all implementations: see the Flavia chapter of The XXICC Anthology rev 0.0q which has an updated version of Flavia: the Free Logic Array. XXICC (21 ...
Dear All,   I am very very new learner of VHDL code. I am interested to learn hoe to read an image by VHDL code.   My target is to develop an image edge detector.   Thanks ...
This blog is part 3 of a 4 part series of implementing a gradient filter on an FPGA.  If you have not already read the earlier parts see the link below to get up to speed before reading this blog.  Additionally the user can catch some of our previous blog posts, linked below.  Part 1 and 2 of this blog series Gradient Filter implementation on an FPGA - Part 1 Interfacing an FPGA with a camera Gradient Filter implementation on FPGA : Part 2 Implementing gradient Filter   Ot ...

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