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2017

Let's try to do something real with the Xilinx Spartan-6 FPGA: write a set of data to an SD card.

 

To boost the FPGA skills, I'm refreshing theory and checking out some real designs.

For a standalone XuLA2 board, talking to SD cards is a good practical example.

 

There's  a Micro SD slot on the XuLA2 models. The only other component you need is a spare Micro SD card.

 

Don't use an SD card with your marriage photo shoot on it. You'll very likely loose that when you test this project.

 

The Xess XuLA2 github has two SD card projects. We'll use the SD Card Control Test example.

In this project, the FPGA has two main duties:

  • Read and Write SD data
  • Communicate with your PC over USB

A python script on your PC will generate test data and send it to the FPGA over USB.

The FPGA writes the data to your SD card. We're using low level protocol here, no filesystem.

When finished, it reads the data back off the SD card and verifies the results.

 

VHDL Libraries

 

Xess made a set of common VHDL libraries. The example uses several those libs.

The communication with the SD slot is via :

  • SDCard.vhd

Clocking is handled by these two:

  • ClkGen.vhd
  • SyncToClk.vhd

Talk to the PC over USB happens with this one (and the on-board PIC microcontroller):

  • HostIo.vhd

These libs are not only useful, but also a great source to learn reusable VHDL.

 

 

How it Works

 

The XESS blog explains the example in detail. It explains both the electrical connections and how the Micro SD protocol is handled.

The header comments of the SdCard.vhd source file document many implementation details.

Open that file by double-clicking the u3 - SdCardCtrl node in the Implementation view.

If you've ever tried to understand (or port) a microcontroller SDCard lib - maybe the one from Arduino - you'll recognise much of the logic.

 

Let's now synthesize the project and generate the programming file.

Insert the SD card, connect the XuLA2 with your laptop and load the bitstream:

 

xsload --fpga sdcardctrltest.bit

 

Once you've loaded the bitstream, your XuLA2 board sits idle. You need to tell it to read and write data.

There's a python scrip that does exactly that.

If you have retrieved the latest XuLA2 FPGA sources from GIT, you'll find a python file named SDcardTest.py in the project directory.

If you're using the examples that were installed by the XESS installer, you can retrieve the testbed from here:

https://raw.githubusercontent.com/xesscorp/XuLA2/master/FPGA/SdcardCtrlTest/SdcardTest.py

 

Run the script to write a random set of data to the SD card, read it back and check if everything is correct:

 

SDcardTest.py

 

 

The data is written using low level protocol. You will not be able to read the data when you insert the SD card into your PC.

The design doesn't use a filesystem or any other advanced disk management protocol. It's SD access for real blokes.

 

Windows 8 and Windows 10 with Xilinx ISE

 

If you are running WIndows 10 64-bit, you may encounter several ISE problems:

 

  • Pressing the Open Project button (and several other actions, like selecting the Preferences menu item) crashes ISE.
  • Running the Simulator results in a "failed to link the design" message and the simulator not starting.

 

Switching to the 32-bit version has solved most of them for me:

To switch,

  • alter the command in the ISE shortcut to
    "<DRIVE>:\Xilinx\14.7\ISE_DS\settings32.bat D:\Xilinx\14.7\ISE_DS\ISE\bin\nt\ise.exe"
  • in "<DRIVE>:\Xilinx\14.7\ISE_DS\ISE\bin\nt", rename fuse.exe to _fuse.exe, and copy the fuse.exe from the "..\nt64" directory over (got that from here)

 

After that, I still have one issue left: when in Simulator, the Relaunch functionality doesn't work. I have to close iSIM and restart it from within ISE.

 

I've also tested the design with a known defect card - one that's rejected by any known operating system and can't be formatted.

This test was successful. The test flagged that the FPGA wasn't able to write data, as expected:

 

 

The core of the example can be used in your own design as a persistent storage area.

If you want to use it as a data exchange mechanism, you'll have to find a way to read the raw data from the card. That can be done with an Arduino.

Another - advanced - option is to implement a supported file systems (fat32?) in HDL,

Whatever you do, make it a nice design and share your work.

 

 

XuLA2 FPGA - First Impressions of the Development Tools
XuLA2 FPGA - SD Card Read and Write
XuLA2 FPGA - Rotary Encoder and VHDL
XuLA2 FPGA - PWM with Dead Band in VHDL
XuLA2 FPGA - Up the Clock
XuLA2 FPGA - Utility to Generate Pin Assignments

I purchased a Xess XuLA2. It arrived this morning.

This post is the story of my first steps

 

 

I have a little bit of experience with FPGAs. I learned digital electronics in the early-to-mid 80's.
My VHDL skills are beginner level and I've worked with the Xilinx Spartan 6 and development tools.

This is my experience to run a first design on the XuLA2 board

 

I have done training work with the Spartan 6 FPGA before. The Xilinx development environment is running on my laptop and works.

I can focus on getting the Xess tools working.

That's not difficult, but I had some issues with Python dependencies that I'll document here.

 

The USB Driver

Installing the device on a Windows10 laptop was easy. There's the typical 'signed driver' hurdle to jump.

When you plug in the XuLA, it's recognised by the OS, but in the Device Management screen there's a warning next to the device.

The typical Windows " invalid hash signature" warning.

 

The solution is known. You have to restart Windows in a special mode that allows to install unsigned drivers (use your google-fu to find the instructions for your version and language).

Once Windows is restarted in the 'allow unsigned drivers' mode, right-click on the device in the Device Manager and select Update Driver.

Windows will find the driver for you and install it. From then on, all is good.

 

The Loader Tool

The XuLA depends on external tools to synthesize your design into an upload file. I'm using the free Xilinx ISE toolset.

The Xess tools come into play when you want to load your designs to the FPGA.

They have command line and GUI applications. I'm testing the command line Loader tool here.

 

The command line tools are for Python 2.7 - I got synthax errors in the print() and other functions when trying it with 3.x.

The instructions to install the toolkit are here: https://xstools.readthedocs.io/en/python/installation.html.

Install went fine. But I ran into a dependency conflict.

The tools depend on a Python library called pubsub. The installer nicely reports that the minimum required version is pypubsub >= 3.1.2.

(I don't know anything about python - I learned the deep internals of it today while getting all of this working )

The bad thing is that the latest version of that library, 4.x, doesn't work (either with Python 2.7 or with the current Xess tools release - I don't know that).

So I had to force-replace pubsub 4 with pubsub3 (I've logged an issue on github).

 

I used these commands:

 

pip uninstall Pypubsub
pip install -Iv https://pypi.python.org/packages/95/5a/1801be1a63af9250e79b8941a37b88e3ca0d660b880b9862fe9016ae6a3a/PyPubSub-3.3.0.zip

 

Finding all of that out took me a half day - don't ask how I did that unless we're in a pub together and you're paying for the drinks.

Once done, all works.

 

C:\Python27>xstest
Success: XuLA2-LX25 passed diagnostic test!

 

 

Testing the XuLA2

I used the mandatory blinky project. I didn't use an LED though, but an oscilloscope.

 

The XuLA2 examples are available when you install the Xess XSTOOLS.

I've opened Examples/XuLA2/LX25/blinker in the Xilinx ISE, synthesised it and generated the programming file.

You can also make the project yourself by following the instructions in the Xess tutorial, chapter "Starting a Design in WebPACK"

 

Then I used the XSTOOLS Loader to beam it to the XuLA2:

 

xsload --fpga blinker.bit
Success: Bitstream in blinker.bit downloaded to FPGA on XuLA2-LX25!

 

 

With my scope attached to the CLK pin at the right lower corner of the PCB, I got the output:

 

 

The clock and output setting are defined in blinker.ucf:

 

net clk_i     loc=a9;  # 12 MHz input clock.
net blinker_o loc=t7 | IOSTANDARD=LVTTL | DRIVE=24 | SLEW=SLOW ;  # Blinker output to LED.

 

 

 

The downcount from 12 MHz clock to approx. 1Hz blink signal is done in the VHDL design:

 

entity blinker is
    Port ( clk_i : in  STD_LOGIC;
           blinker_o : out  STD_LOGIC);
end blinker;


architecture Behavioral of blinker is
signal cnt_r : std_logic_vector(22 downto 0) := (others=>'0');
begin


process(clk_i) is
begin
  if rising_edge(clk_i) then
    cnt_r <= cnt_r + 1;
  end if;  
end process;


blinker_o <= cnt_r(22);


end Behavioral;

 

(if only e14 had a VHDL syntax highlighter)

 

Summary

It works

 

 

 

XuLA2 FPGA - First Impressions of the Development Tools
XuLA2 FPGA - SD Card Read and Write
XuLA2 FPGA - Rotary Encoder and VHDL
XuLA2 FPGA - PWM with Dead Band in VHDL
XuLA2 FPGA - Up the Clock
XuLA2 FPGA - Utility to Generate Pin Assignments

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