The XuLA2 standard runs on a 12 MHz clock. That's plenty for many things, but not enough for some designs.
In my PWM with DeadBand project, for instance, the effective signal frequency that the module outputs is halved for each bit of precision of the duty cycle register.
If you want to have 256 steps between 0 and 100% duty cycle, you need 8-bit precision and your maximum PWM output frequency is 47 kHz. When you need higher PWM frequency with the same duty cycle granularity, you can use a Digital Clock Manager to generate a (much!) faster clock signal for the PWM module.
I need a minimum 1 MHz output for the GaN half-bridge that I'm driving (an LMG5200). The deadband should be a in the range of 8 - 10 ns.
Let's assume that we allow for 2 ns steps (we can then set a deadband of 10 ns by skipping 5 ticks.
2ns means that our input frequency has to be 500 MHz. We can't do that - its beyond the capabilities of the Digital Clock Manager of the Spartan-6.
4ns is doable but a stretch. It'll require an up-sample to 250 MHz.
Only 12 MHz! Now what
That's the title of the Xess VHDL Tutorial chapter that covers this concept. Look there for the explanation.
I'll focus on a practical application.
library UNISIM; use UNISIM.VComponents.all; -- ... architecture Behavioral of Rotary_Pwm is -- ... signal clk_fast : std_logic; begin DCM_SP_inst : DCM_SP generic map ( CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32) CLKFX_MULTIPLY => 22 -- Multiply value on CLKFX outputs - M - (2-32) ) port map ( CLKFX => clk_fast, -- 1-bit output: Digital Frequency Synthesizer output (DFS) CLKIN => clk_i, -- 1-bit input: Clock input RST => '0' -- 1-bit input: Active high reset input ); u0 : PwmDeadBand port map ( clk_i => clk_fast, duty_i => accumulator_s, band_i => 64, pwmA_o => pwmA_o, pwmB_o => pwmB_o ); -- ...
The DCM_SP_inst is an instance of the Spartan-specific DCM_SP primitive. It's not a standard VHDL construct.
At this point, our design becomes device dependent. You can't just port it to another FPGA.
I've used the following design decisions:
To get the 4ns step rate the minimum frequency is 1/4ns = 250 MHz.
Our output frequency is going to be that frequency divided by 256, so we're just under our MHz output goal.
We'll have to up it to at least 256 MHz.
With a 12 MHz clock as input, we'll need to multiply that clock with 22 and get 264 MHz.
Each step will have a period of 3.8 ns - close enough to the 4 ns we're aiming for.
We only have to pass that fast clock to the PWM module.
There's no reason to route it to the rotary encoder, it can keep running on the 12 MHz clacker.
photo: Bart Simpson looks over a wall
In the capture above, I've set a deadband of 64 clock ticks (to have something measurable on the scope).
The signal frequency is 1.03127 MHz (theoretical 12 MHz * 22 / 256 = 1.031250 MHz)
The time between the cursors is 244 ns for 64 dead band ticks. So the measured granularity of our deadband is 244ns / 64 = 3.8125 ns.
Here's a capture with 8 clock ticks.
My GaN board will run with 2 or 3 ticks - I'd have to use different probe technique to show that.
Good captures in the neighbourhood of 8 ns (that's the deadband that I'll try to achieve) are hard on a 50 MHz scope
|XuLA2 FPGA - First Impressions of the Development Tools|
|XuLA2 FPGA - SD Card Read and Write|
|XuLA2 FPGA - Rotary Encoder and VHDL|
|XuLA2 FPGA - PWM with Dead Band in VHDL|
|XuLA2 FPGA - Up the Clock|