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2017

I have been chosen as a roadtester for DEO-NANO P0082 and my kit has arrived. I decided before going roadtest project, it will be nice to give a heartbeat and step into FPGA world. Before you go reading, I want to say I am not an FPGA expert but I want to be one   I just had a course during my master. If you confused something or think something is wrong, please do not hesitate to leave a comment.

 

Let's start with what is FPGA? To be honest it is a hard question and I will answer in some extent. FPGA stands for Field Programmable Gate Arrays so the name suggests we can program(configure) FPGA after the fabrication. FPGA is not a microcontroller or microprocessor but you can design a microprocessor on FPGA. Basically, it is a reconfigurable device and you can design any digital circuit on FPGA with its hardware limitations.

 

Let's see how we program an FPGA? Well, when I say programming FPGA, we don't write a software program. We do design a hardware with hardware description languages(HDL). The most two popular languages are Verilog HDL and VHDL (V stands for very high speed integrated circuit). I don't go into which one is better than other because I don't know the answer. I can say it is not easy to program an FPGA as microcontrollers. It is more complicated and harder but this doesn't mean we shouldn't play with it.

 

Why do we use FPGA we have such a great microcontrollers with affordable prices? Microcontrollers are manufactured for general usage but FPGA is a custom designed.

 

- Microcontroller is manufactured for general usage but FPGA is a custom designed.

- Microcontroller works instruction by instruction but FPGA works concurrently so it is nature is parallel

 

I think these two are the main reasons which led other advantages like speed and flexibility. Hence, FPGA is concurrent as nature it will be faster than a microcontroller if designed properly. There for it is used highly in the military, telecommunication, and R&D. My project will be implementing AES on FPGA and see the advantages. I didn't use AES before. I know it can be hard and time is limited. If I can't complete on time, I will represent another project which is different types of multiplier circuits. It is a multiplier, how many types can be? Well, there are different types. Some are optimised for speed some are space. If I have time, I will implement both.

 

I think I mixed up many things Let's unbox the DEO-NANO P0082.

IMG_20170730_131708.jpg

This is the box of the kit arrived in Element14 cardboard with shiny bags which are at the background. I really like the bags. They are so shiny

IMG_20170730_131835.jpg

It includes DEO-NANO FPGA board, an extendable mini USB cable, and some brochures

. IMG_20170730_131941.jpg

This image can give an idea about the size of the board. It is a little smaller than a credit card.

This is the power-on test. Just unbagging the DE0 nano and plug it to PC, you will see the LEDs are flashing.

 

Initial thoughts:

Positive:

The kit looks handy.

Negative:

The quick start guide says there are two CDs inbox but I think they are not sending CDs anymore but not updated the quick start guide. Actually, I don't want CDs but if it says, they should be inbox.

  If your looking to get into FPGA development and have been following my blogs, this is probably the post that you should pay most attention to as it's likely to make clear the design process.

 

So far I've followed the quick start guide,  downloaded the recommended software and installed the demo bitstreams onto the deo-nano development board. For clarification, a bitstream (or bit stream) is the name of your compiled project that gets transferred onto the FPGA device.

 

Now it's time to follow the my-first-fpga guide to create my first ever FPGA project, its a foolproof step by step guide which takes us from the very beginning of making a project through to downloading that compiled project onto the deo-nano development board.

 

Forget any other software that comes with the board, all were interested in is the Altera Quartus2 design suite, this has everything we need including a compiler and hardware programmer. This one thing does it all.

 

Here's a quick run through of the steps used to develop an FPGA application:

 

1) Create a project with the wizard, giving it a name and telling it which FPGA you are using.

2) Add a Block Diagram/Schematic to the project (this is similar to a schematic editor on PCB design software where components can be added, moved and connected with wires)

3) The objects on the schematic are created by using a programming language called Verilog HDL, it has similarities to other programming languages.

4) Once an object has been created in Verilog HDL, it shows up as a symbol on the schematic. Wires can be connected between these objects using inputs and outputs described in the programming.

5) Symbols of input / output pins are created on the schematic to represent the physical pins to allow interaction with the real world. These can be connected to the inputs/outputs of our object.

6) The input/output pin symbols are given names, a pin planner allows us to point those names to the physical pins on the fpga.

7) Compile the project.

8) program the bitstream (the output of the compiler) onto the fpga

 

Ok, there are a couple of other bits but thats a general overview and hopefully it outlines the process that people new to FPGA's can understand. Its basically very similar to making a circuit diagram in a pcb design package. Where the components have internal functions defined by a programming language. Anybody who used Javabeans and played with the Beanbox will be very comfortable using this!

 

So lets first look at the Block Diagram/Schematic view

 

schem1.jpg

 

 

 

 

This is the completed schematic for my project, The object in the top right labelled "simple_counter" is an object that I made in Verilog HDL following an example whereas the other two main objects are pre-made objects that Altera provides (A wizard can help set them up and tailor them for your needs).

 

Coming out of the right hand side of "simple_counter" is a wire labelled "counter", Because the wires going into the left of the "counter_bus_mux" are also labelled "counter" these are all symbollically linked so its as if all of those wires are connected to each other.

 

The smaller objects labelled "CLOCK_50", "KEY[0]" and "LED[3..0]" are all symbollic of physical pins on the fpga, these get assign or mapped to real life pins later in the process.

 

 

 

 

 

 

vhdl.jpg

 

 

 

 

 

Here's the Verilog HDL code that went into making the "simple_counter" object in the schematic above, as you can see it has an input and a output described, you can see these displayed in the schematic above. Notice how the structure is similar to other programming languages and it's pretty easy to follow.

 

Once this object has been saved we can add it to the schematic and link other objects to it, the design suite draws the object for us, we don't need to do anything like that ourselves.

 

 

 

 

 

pinassign.jpg

 

 

 

 

 

 

 

 

Once our schematic is complete, its time to launch the Pin Planner. If you look at the table at the bottom of the Pin Planner under node names, we can see the names of the input/output pins in our schematic above. In the location box is where we assign the pin in the schematic to the desired pin on the physical FPGA. In this picture, I double clicked the location box for "CLOCK_50" and a drop down list of all of the pins on our fpga device appeared. I selected PIN_R8 which is a dedicated clock pin, so looking back at the schematic we can see that CLOCK_50 is going to be turned on and off by a clock source on the fpga.

 

 

 

 

 

 

 

 

 

 

 

pinassigncomplete.jpg

 

 

 

 

 

 

 

 

 

 

 

 

Heres the completed pin assignment. This can be opened up at anytime during the design process to assign new input/output pins.

 

 

 

 

 

 

 

 

 

 

 

 

Once this is done your project is finished and its simply a case of clicking the compile button, plugging the de0-nano into a USB port and copying the compiled bitstream program onto the fpga using the programmer in the design suite. I have included any pictures for the process as it really is simple and self explanatory. There are pictures and a step by step guide in the my-first-fpga document but I have included a picture of the compiler report that was generated:

 

compilereport.jpg

 

 

 

 

 

 

 

As you can see, very few of the fpga's resources were used to make this project.

 

 

 

 

 

 

 

 

 

I'm going to try and explain the schematic (and hopefully get it right).

1) An external clock source is fed into a PLL(phase locked loop) element. This takes a 50mhz clock which is pulsing this pin on/off and slows it down. The output of this PLL goes into the simple counter, the single output of this counter is symbolic of a 32bit bus. The counter element itself increments the 32bit bus like it would a 32bit variable. From that 32-bit bus, just 8 of those bits are fed into the "counter_bus_mux". Im not sure exactly how that part works but it takes the data from those 8-bits and converts it into 4bits then displays it onto 4 led's.

 

Hopefully I got that right, if not then please feel free to explain better in the comments below!!

 

Heres a quick video of the results of this project:

 

 

And that's it for today! Tomorrow Im going to go Lone Ranger and try to get this binary counter displaying on all 8 LED's rather than just 4 before I get bogged down reading the full user manual.

 

Oh! Maybe I should mention that I completed this project in under an hour, there appears to be a lot to it but realistically it was easier than I anticipated!!

This post covers my experiences working through the quick start guide and moving on from there.

 

Installing The Software

 

All of the required software can be downloaded from http://de0-nano.terasic.com/cd I was required to register at terasic.com to download their software. Downloading the terasic cd and other bits from there was as simple as downloading a regular file. There are links from there to the Altera website where I found the Quartus2 design suite. Of course I had to register with Altera too to download this software.

 

At the Altera website, there are 3 different packages you can choose from. There's a lite edition which includes support for the cyclone4 that we will be using, theres a web edition which I chose to download for the time being and there's a premium edition which includes a larger range of fpga's and requires people to purchase a license to use. The first 2 options don't require any such license.

 

The Altera software is available for Windows or Linux, usually I would use a Linux version when there's a choice but the Terasic software has some Windows .exe files only so since I'm learning a new technology I decided to make things easier on myself and boot up my trusty old copy of Windows XP, maybe once I'm more familiar with the device I'll move over to Linux with it.

 

The final part of installing the software was to install the USB Blaster Driver. This is the device driver that your PC uses to talk to the FPGA board, unfortunately the quick start guide doesn't run through how to do this. After some investigating I found that the driver is included in the Quartus2 software that was downloaded and there are instruction for how to install it here https://www.altera.com/support/support-resources/download/drivers/dri-index.html in particular its the "USB-Blaster Cable" links you want to follow.

 

(later on I also found instructions for installing the device driver in the "my first fpga" document)

 

Using The Demonstrations

 

The demonstrations that come with the Terasic cd are easy to install onto the board (once you have the driver installed!). Simply locate the relevant .bat file while the development board is connected to your pc and it flashes automatically, so all of this seems simple enough and were at the end of the quick start guide. I'll need to look further into the documentation to find out how to make such a mysterious .bat file!

 

The final part of that guides suggests reading the user manual on the cd to learn more, while looking for that I noticed another file in the same directory called "DE0-Nano_My_First_Fpga_v1.0.pdf" and so decided to take a look at that first. I'm sure glad I did!!

 

Moving On From The Quick Start Guide

 

my1stfpgafront.jpg

my1stfpgapage1.jpg

 

 

 

 

 

 

 

 

Page 1 of this guide really seems to put me at ease, it just explains the process of FPGA design in a simple to understand way. I suppose part of the difficulty of getting into a technology like FPGA's is the fear of the unknown and the assumption that it's going to be really complicated. To have the process explained in such a simplistic and clear way has taken away a lot of my apprehension.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

my1stfpgapage7.jpg

 

 

 

 

 

 

 

Page 7 describes what the rest of this guide is all about, its basically a complete step by step guide to making a project with the Quartus2 design suite, it teaches you how to create a counter which displays on the LED's of the development board. Once the project is finished it guides us through the whole compilation process and then shows us how to get this compiled project onto the FPGA development board itself so we can see it in action.

 

 

 

 

 

 

 

 

 

 

 

Thats as far as Ive got today, it's time to kill some aliens on XCOM2!!

 

Positive Comments

 

So far my experience with this development kit has been greatly enhanced by the documentation which is easy to follow and is filling me with confidence that I will be up and running with FPGA development faster than I originally thought.

 

Negative Comments

 

The only negative thing I could say is that there should be more explanation on where from and how to install the device driver in the getting started guide, its impossible to flash the demonstrations onto the development board without it.

 

Suggestions

 

The My-First-fpga guide seems to be the valuable document needed towards learning the foundations of how to develop for this board and is a great asset to Terasic. It would be a great advantage if this guide was included in a printed format with the development kit, if using a single monitor it's soon going to get frustrating switching screens to follow the guide. I also believe such a thing would make a useful quick reference manual for people to keep handy.

 

For now though it's lucky Ive got a tablet to work from!!

box.jpg

 

Recently I was selected to roadtest the terasIC DEO-NANO P0082 fpga development kit. My application was based around reviewing the P0082 for suitability as an entry level device to simplify the process of people wanting to explore fpga development for the first time.

 

As part of that roadtest application I offered to post regular blogs here in the fgpa group on element14 documenting my progress, this first post centered around the unboxing and first impressions.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

contentsout.jpg

 

The Box Contains:

            - P0082 development board

            - Mini USB cable

            - Quick start guide

            - Brochures for other products

 

I always like getting brochures for other products!!

 

 

 

 

 

 

 

 

 

 

 

 

 

guidefront.jpgguideback.jpg

 

Quick start guide

 

Page 1 has a picture of the P0082 development board with labels to highlight the specific components.

Page 2 contains a brief introduction and a list of relevant software you will need to install to develope with the P0082.

Page 3 is an overview of the pre-loaded demonstration and links of where to download further demonstrations.

Page 4 looks at a control panel demonstration and a system builder tool to enable quick development on the P0082 (I'd imagine a project setup wizard).

 

boardtop.jpgboardbottom.jpgboardside.jpg

 

The P0082 development board looks well made, comes with a clear acrylic protective top cover and has standoffs to raise the bottom of the board from the surface its stood on which is a nice touch. The main component of the board is an Altera Cyclone 4. From what I understand at the moment, the Altera fpga loses all of it's configuration when power is removed and re-configures itself using an external EEPROM. To the left hand side of the board there is an I2C EEPROM so I'm assuming that this is where your compiled program (is that what you call it?) is downloaded from your computer onto ready for the fpga to read upon next power up.

 

Positive Comments

 

The development kit looks reasonably well presented, the quickstart guide is easy to follow and gives me confidence that the product is a worthy contender as an introductory device to the world of fpga's

 

Negative comments

 

One of the pins for the external power header is slightly bent, this coupled with the box looking rather worn and the software cd's that are supposed to be included are missing leads me to think this is a pre-used kit. Keep in mind though that this product was sent as a roadtest product and not one that has been purchased as new. Luckily the software packages can be downloaded easily enough so the missing cd's aren't a huge problem. Fingers crossed the board does function, I'll find out in due time!!

(edit) *after a quick power-up test, the P0082 is working fine and preloaded with the flashing led demo.

 

 

bentpins.jpg

 

* Pictures taken with my new general purpose camera Canon EOS 750D

This post is a preparation for my attempt to generate VGA with a XuLA2 FPGA board.

I'm generating an image file that I can upload to the board's SDRAM.

The FPGA will read it from the RAM and convert it into a VGA image.

 

The example project for the VGA plug-in for the XuLA has an example image.

The latest loader tool for the board (xsload 0.1.31) doesn't support the format of that file.

There's an older version of the loader that supports it but doesn't want to run on my pc.

Not to worry. In this post I convert the image to a supported load format: Intel HEX.

 

The XuLA FPGA VGA project and the image file are available on the Xess github:
https://github.com/xesscorp/StickIt/tree/master/modules/Vga/FPGA/PixelVgaTest

 

 

Preparation - Generate Binary Image

 

The example image is in a proprietary format. Below are a few lines as exampe

 

+ 10 00000000 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C
+ 10 00000010 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C
+ 10 00000020 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C 7F 2C

 

10 stands for 0x10 data elements (16 bytes), the second field is the address in ram it has to go, then there's the 16 bytes payload that represent a few pixels of the image.

 

The easiest path from that file to the somewhat elaborate Intel HEX format is to convert this into a binary file that only contains the pixel data.

There are existing utilities that can convert bin to Intel HEX.

 

I made a small c++ utility to grab those pixel bytes from that example and write it to a binary file.

The fixed filenames, not using a data buffer and the way I did the ascii-hex to number conversion show that I'm in a holiday mood.

 

//============================================================================
// Name        : xess_file_converter.cpp
// Author      : Jan Cumps
// Version     :
// Copyright   : copyleft
// Description : Convert XES images to BIN files
//============================================================================


#include <iostream>
#include <fstream>
#include <string>
#include <sstream>


using namespace std;


int main() {


    ifstream inFile("D:\\users\\jancu\\Documents\\elektronica\\xess\\master\\StickIt\\modules\\Vga\\FPGA\\PixelVgaTest\\img_800x600.xes");
    ofstream outFile ("D:\\users\\jancu\\Documents\\elektronica\\xess\\master\\StickIt\\modules\\Vga\\FPGA\\PixelVgaTest\\img_800x600.bin", ios::out | ios::binary | ios::trunc);
    string subs;
    uint32_t uToken = 0U;
    char c;
    uint16_t uVal;

    string line;
    while (getline(inFile, line))
    {
    uToken = 0U;
        istringstream iss(line);
        while (iss >> subs) {
        if (uToken > 2) {
        stringstream ss;


        ss << hex << uppercase << subs;
            ss >> uVal;
            c = uVal;
            outFile.write(&c, 1);
        }
        uToken++;
         }
    }


    outFile.close();
    inFile.close();


return 0;
}

 

The result is a file that has 800 * 600 * 2 bytes. Checked with the file size:

 

 

 

Generate Intel HEX File

 

The sourceforge.net srecord project supports converting binary files into Intel HEX format.

 

 

srec_cat img_800x600.bin -binary -o img_800x600.hex -intel

 

The output format generated by the utility is as below:

 

:020000040000FA
:200000007F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C30
:200020007F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C7F2C10
...
:20A5C00000000000000000000000000000000000000000000000000000000000000000007B
:20A5E00000000000000000000000000000000000000000000000000000000000000000005B
:00000001FF

 

 

The xsload utility seems (I can't prove it yet because I don't have a VGA cable) to accept the format and load the file to RAM:

 

xsload  --ram img_800x600.hex

 

output

 

Success: Data in None downloaded to RAM on XuLA2-LX25!

 

 

Success?

 

I will know that once I connect the kit to a TV. I've checked the VGA output on an oscilloscope.

I built and loaded the Xess VHDL example (I'll explain the steps in a future blog) and loaded the bitstream:

 

xsload --fpga pixelvgatest.bit

 

output

 

Success: Bitstream in pixelvgatest.bit downloaded to FPGA on XuLA2-LX25!

 

 

Yellow: HSYNC

Cyan: VSYNC

Magenta: one of the video signals

 

 

I hope to be able to show a TV screen with image soon. Hang on ...

 

XuLA2 FPGA - First Impressions of the Development Tools
XuLA2 FPGA - SD Card Read and Write
XuLA2 FPGA - Rotary Encoder and VHDL
XuLA2 FPGA - PWM with Dead Band in VHDL
XuLA2 FPGA - Up the Clock
XuLA2 FPGA - Utility to Generate Pin Assignments

I purchased a Xess XuLA2 FPGA kit a while ago.

As preparation for a test with its VGA module , I'm trying out one of the utilities to automatically create pin mappings.

 

You can plug XuLA modules into several connectors. Based on your choice, you have to route your signals to the FPGA balls that are connected to the pins of that connector.

And: Mapping FPGA pins to connector locations can be a dog.

 

 

I found out yesterday that there is a utility to perform this much dreaded task: the Pin Assignment Generator.

 

 

Manual Pin Mapping

In an FPGA project, you define* the mapping between I/O signals and FPGA balls in a constraint file.

If you are writing for a project with a fixed layout, that's a one-off task.

With flexible kits (like the XuLA and its motherboard, where you can plug modules in different ports) things are different.

You'd have to look up the mapping between the connector you use and the FPGA I/Os. Then adapt the constraint file with the appropriate links.

The documentation has all info that's needed. But it's a tedious job.

 

 

Mapping Utility

Tedious work calls for automation. And there's good news.

There's a mapping utility xsconnect available for the XuLA family.

It's a Python script that does  the whole cross-ref. It knows all XuLA products and their pinouts.

Based on your combination (what is plugged where in which motherboard for what FPGA board), it generates a ready-to-go mapping list.

 

In my case, I'm using a VGA module, plugged in connectors 2 and 3 of a motherboard version 4, running on an FPGA board version 2 .

I throw that combination to the utility, and it kindly creates the entries:

 

xsconn -p "StickIt! VGA V2" -m "StickIt! V4" -n pm2+pm3 -d "XuLA2"

 

output:

########################################################################
# StickIt! VGA V2 ==[pm2+pm3]==> StickIt! V4 ==> XuLA2
net b2      loc = c1;
net b3      loc = j4;
net b4      loc = k3;
net g1      loc = b2;
net g2      loc = e1;
net g3      loc = h1;
net g4      loc = r1;
net hsync_n loc = r2;
net r2      loc = f1;
net r3      loc = m1;
net r4      loc = m2;
net vsync_n loc = t4;
########################################################################

 

You can then paste that in your constraint file and adapt the signal names to your design.

If your design uses the same signal names as the ones in the utility, you can just cut and paste.

 

Here's the relevant snippet of a constraint file I adapted for the above combination:

# Horizontal & vertical syncs.
net hSync_bo        loc = r2;
net vSync_bo        loc = t4;

# Red, green, blue color components to VGA DACs.
net red_o<1>        FLOAT;
net red_o<2>        loc = f1;
net red_o<3>        loc = m1;
net red_o<4>        loc = m2;
net green_o<0>      FLOAT;
net green_o<1>      loc = b2;
net green_o<2>      loc = e1;
net green_o<3>      loc = h1;
net green_o<4>      loc = r1;
net blue_o<0>       FLOAT;
net blue_o<1>       FLOAT;
net blue_o<2>       loc = c1;
net blue_o<3>       loc = j4;
net blue_o<4>       loc = k3;

 

 

Where Next?

 

To get the utility, execute this command from your Python enabled computer:

 

easy_install xsconnect

 

It's open source. The version created by Xess supports all their FPGA boards, motherboards and plug-ins.

But it's extendable if you want. You can add your own designs, or use it in a completely different context where flexible FPGA pin mapping is needed.

 

* generalisation. There are other options

 

 

XuLA2 FPGA - First Impressions of the Development Tools
XuLA2 FPGA - SD Card Read and Write
XuLA2 FPGA - Rotary Encoder and VHDL
XuLA2 FPGA - PWM with Dead Band in VHDL
XuLA2 FPGA - Up the Clock
XuLA2 FPGA - Utility to Generate Pin Assignments

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03-dev-kit.jpg

 

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01-full-hd-camera.jpg

 

We have shared with people some of the features on hacker/maker community.

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