If your looking to get into FPGA development and have been following my blogs, this is probably the post that you should pay most attention to as it's likely to make clear the design process.
So far I've followed the quick start guide, downloaded the recommended software and installed the demo bitstreams onto the deo-nano development board. For clarification, a bitstream (or bit stream) is the name of your compiled project that gets transferred onto the FPGA device.
Now it's time to follow the my-first-fpga guide to create my first ever FPGA project, its a foolproof step by step guide which takes us from the very beginning of making a project through to downloading that compiled project onto the deo-nano development board.
Forget any other software that comes with the board, all were interested in is the Altera Quartus2 design suite, this has everything we need including a compiler and hardware programmer. This one thing does it all.
Here's a quick run through of the steps used to develop an FPGA application:
1) Create a project with the wizard, giving it a name and telling it which FPGA you are using.
2) Add a Block Diagram/Schematic to the project (this is similar to a schematic editor on PCB design software where components can be added, moved and connected with wires)
3) The objects on the schematic are created by using a programming language called Verilog HDL, it has similarities to other programming languages.
4) Once an object has been created in Verilog HDL, it shows up as a symbol on the schematic. Wires can be connected between these objects using inputs and outputs described in the programming.
5) Symbols of input / output pins are created on the schematic to represent the physical pins to allow interaction with the real world. These can be connected to the inputs/outputs of our object.
6) The input/output pin symbols are given names, a pin planner allows us to point those names to the physical pins on the fpga.
7) Compile the project.
8) program the bitstream (the output of the compiler) onto the fpga
Ok, there are a couple of other bits but thats a general overview and hopefully it outlines the process that people new to FPGA's can understand. Its basically very similar to making a circuit diagram in a pcb design package. Where the components have internal functions defined by a programming language. Anybody who used Javabeans and played with the Beanbox will be very comfortable using this!
So lets first look at the Block Diagram/Schematic view
This is the completed schematic for my project, The object in the top right labelled "simple_counter" is an object that I made in Verilog HDL following an example whereas the other two main objects are pre-made objects that Altera provides (A wizard can help set them up and tailor them for your needs).
Coming out of the right hand side of "simple_counter" is a wire labelled "counter", Because the wires going into the left of the "counter_bus_mux" are also labelled "counter" these are all symbollically linked so its as if all of those wires are connected to each other.
The smaller objects labelled "CLOCK_50", "KEY" and "LED[3..0]" are all symbollic of physical pins on the fpga, these get assign or mapped to real life pins later in the process.
Here's the Verilog HDL code that went into making the "simple_counter" object in the schematic above, as you can see it has an input and a output described, you can see these displayed in the schematic above. Notice how the structure is similar to other programming languages and it's pretty easy to follow.
Once this object has been saved we can add it to the schematic and link other objects to it, the design suite draws the object for us, we don't need to do anything like that ourselves.
Once our schematic is complete, its time to launch the Pin Planner. If you look at the table at the bottom of the Pin Planner under node names, we can see the names of the input/output pins in our schematic above. In the location box is where we assign the pin in the schematic to the desired pin on the physical FPGA. In this picture, I double clicked the location box for "CLOCK_50" and a drop down list of all of the pins on our fpga device appeared. I selected PIN_R8 which is a dedicated clock pin, so looking back at the schematic we can see that CLOCK_50 is going to be turned on and off by a clock source on the fpga.
Heres the completed pin assignment. This can be opened up at anytime during the design process to assign new input/output pins.
Once this is done your project is finished and its simply a case of clicking the compile button, plugging the de0-nano into a USB port and copying the compiled bitstream program onto the fpga using the programmer in the design suite. I have included any pictures for the process as it really is simple and self explanatory. There are pictures and a step by step guide in the my-first-fpga document but I have included a picture of the compiler report that was generated:
As you can see, very few of the fpga's resources were used to make this project.
I'm going to try and explain the schematic (and hopefully get it right).
1) An external clock source is fed into a PLL(phase locked loop) element. This takes a 50mhz clock which is pulsing this pin on/off and slows it down. The output of this PLL goes into the simple counter, the single output of this counter is symbolic of a 32bit bus. The counter element itself increments the 32bit bus like it would a 32bit variable. From that 32-bit bus, just 8 of those bits are fed into the "counter_bus_mux". Im not sure exactly how that part works but it takes the data from those 8-bits and converts it into 4bits then displays it onto 4 led's.
Hopefully I got that right, if not then please feel free to explain better in the comments below!!
Heres a quick video of the results of this project:
And that's it for today! Tomorrow Im going to go Lone Ranger and try to get this binary counter displaying on all 8 LED's rather than just 4 before I get bogged down reading the full user manual.
Oh! Maybe I should mention that I completed this project in under an hour, there appears to be a lot to it but realistically it was easier than I anticipated!!