So far the DE0-NANO P0082 development board and the associated user guides have given me a basic overview on how to develop with FPGA's and introduced me to a simple Verilog HDL file. To move forwards in FPGA development I would need to learn more about Verilog HDL and while Terasic have done a great job creating resources that teaches the basics of development I wouldn't expect them to provide me with a full Verilog HDL learning resource and so I looked elsewhere.

 

The first resource I found on Google was at http://www.asic-world.com/verilog/index.html and so I spent some time looking through their tutorials and examples, as with most new things I'm learning I find it useful to learn the basics and take a few days break. When I come back to the subject I find myself more able to understand what I'd learn previously and also learn more as I go.

 

After having a few days break, I decided to alter the files for the bitstream I made in Part 3 of this blog series. My intention was to create an 8-bit counter that displays on the LED's and the ability to change the direction of counting when one of the user buttons are pressed. Here is my new board layout :

 

board.jpg

 

In the board layout you can see I kept the pll to provide the clock source, the simple_counter module now has an additional button input and Ive removed the multiplexer, choosing to output 8 bits from the counter bus straight to LED's.

 

Before we look at the Verilog file for the simple_counter component lets investigate that counter bus a little bit more in depth. The counter bus is a single trace here but its representing a 32 bit bus with 32 wires, so here we've connected wires 18,19,20,21,22,23,24 and 25 to LED's and left the others disconnected. Its possible to connect a consistent range of 8 wires from anywhere in this bus and the LED's will still show an 8 bit counter.

 

Whats really going on is that simple_counter actually outputs as a 32-bit counter on that bus and were selecting a range, if we select a range of 0,1,2,3,4,5,6 and 7 the counter will be running so fast as thats where the least significant bits are that we won't see the LED's change (they'll just appear constantly on) and if we select the range 24,25,26,27,28,29,30 and 31 the LED's will count too slowly this is because as we move up the range the speed of the bits changing becomes less frequent.

 

It's entirely possible to just get the simple_counter component to output an 8-bit bus rather than a 32-bit one and alter the pll to change its counting speed to one that would be more suitable but I just left this one in for well, who knows why I left it in, it was just there already I suppose!

 

Right lets look at the new Verlog HDL file:

 

simple_counter.jpg

 

I added an extra button input and a new register component. Registers are similar to variables only you declare the size in bits you would like that register to be. So reg [31:0] is like a 32 bit variable and reg[0:0] is a single bit which Im using here like a Boolean to keep track of the direction.

 

You'll notice a new section titled "initial begin" this is a place you can initialise the values of the registers at the beginning of the bitstream launching/simulating.

 

Notice that there's 2 "always" blocks. These are functions that run automatically when their conditions are met. so the statements in the "always @ (posedge BUTTON_1)" block between "begin" and "end" will run automatically whenever a new positive edge is detected on the button (ie. whenever the button is pressed or goes high).

 

Multiple "always" statements are allowed in a component and can all run simultaneously.

 

and thats it for today, see the video below to see this in action