Hi, This is my first blog here in element14 community. I am learning FPGA and totally newbie. I've got a bachelor degree in Mechanical Engineering and finishing my master (hopefully next week is my presentation ) and I learned some MCU by myself and now I am trying to learn FPGA by my own. I've got a Z-turn board from MYIR and bought it for second hand from ebay-kleinanzeige because at that time that was the cheapest option to get a Zynq FPGA development board. This is my first vhdl code as well. I would highly appreciate any feedback and suggestions.

 

The following graph shows the layout of the board. Why starting with the buzzer?? Because I want to start with the FPGA side and the buzzer is connected to the FPGA side of the chip.

First lets find out how the buzzer is connected to the chip. The buzzer is defined as M1 BP in the schematic coming inside the CD of the board. The following shows the circuit.

The above schematic shows we have to control the buzzer with BP signal which is mentioned in pages 3 and 15 of the schematic. If you check them, on page 3, it is connected to pin P18 or IO_L23N_T3_34.

I do not know about buzzers as well. Some googling let me guess that if we send 10 Khz signal to it should sound something :D.

For start, I created a new Vivado VHDL project and defining the board. You can find the board and constraint files from here. Add the constraint file to the project.

It seems that there is no clock signal on the board for the PL (FPGA side _ Programmable Logic). Therefore I need to use the PS (CPU side_ Processing System) clock signal for the PL as well. So let's start with the PS.

Click on the "Create Block Design" on the left side. Then call it what ever you want. I left it with the default name desing_1. Click on "Add IP" icon which is a "+" sign and search for "ZYNQ7 Processing System".  Then click on "Run Block Automation" and the OK. Then Connect the "FCLK_CLK0" to "M_AXI_GP0_ACLK" and "S_AXI_HP0_ACLK". I am not sure whether they are really required. Because we are not going to use any AXI connection.

Now we have to create the clock signal we where looking for. Right click on the white spaces and  click on create port. Name the port as "clk_pl" standing for clock for PL and set the direction as output and then OK. Then connect the port to the "FCLK_CLK0" as well. Finally it should look like the following.

To check the clock frequency, double click on the PS block, go to Clock configuration. On PL Fabric Clock, you can find the frequency. For me it was 100MHz. You can disable the other clock if you don't need it.

Now on the "source" window, right click on "design_1" and click on "Create HDL Wrapper" and choose the first option to let us edit it.

Now we have to decrease the clock speed to 10KHz and connect it to the buzzer. So click on "Add or Create Sources" then "add design sources" then  "Create files". I named it "buzzer" and chose VHDL as the file type. Then Ok.

Add "bz_clk" as input and "bz_out" as output. Complete it as the final file would be similar to

You can find the code here. It simply slows down the input cloud.

 

Now we have the buzzer code, we have to modify the wrapper to include inside the project. Go back the "design_1_wrapper". First of all remove line "CLK_PL : out STD_LOGIC" from the entity. It should be in line number around 16. Then add "BP : out STD_LOGIC;" instead inside the entity.

We have to add the buzzer component and connect it with the clock. The final code should look like the code here.

Basically, on line 81, it is connecting the CLK_PL to internal signal s_clk_pl that is defined few line above. And the on line 107, it connects the signal to the buzzer clock signal and then connect the output of the buzzer module to "BP" signal.

Now go to the constraint file. In the "Sources" window, "Constraints". Open the XDC file. We do not need most of the constraints. You can comment all of them, except the following lines:

 

set_property PACKAGE_PIN P18 [get_ports BP]
set_property IOSTANDARD LVCMOS33 [get_ports BP]

 

These to line connect the BP signal to pin P18 of the FPGA using LVCMOS33 standard.

 

Now the project is ready to generate the bitstream. Click on "Generate bitstream" on the left side. This can take while depending on your PC configuration.

I am using Xilinx Platform Cable USB DLC9G for programming. Connect the board using the Jtag and power up the board maybe using USB cable. Click on "Open Hardware Manager" . Then "Open target" and "Auto Connect" and finally "Program Device". Choose "design_1_wrapper.bit" and program. After the programming is finished, The buzzer should make a constant noise like this:

All the project files are here.