Recently I discovered a clever way in MATLAB to interact with my HDL IP cores in situ, running in the programmable logic. Yes, of course, there are many ways to probe logic in an FPGA, but this one is particularly helpful when I need to analyze bits that represents sampled signals.


A few benefits of this method:

  • Simple setup – ARM subsystem is not involved
  • Pass buffers of data to/from MATLAB workspace
  • Post-capture analysis natively in MATLAB (no need to transfer vector files)


With only a JTAG connection to your PC and a little IP block (below) in your Vivado design, you can use the MATLAB HDL Verifier tool to access any AXI-based peripheral in your Xilinx SoC.


This is the MATLAB as AXI Master block. A similar token exists in the Xilinx Vivado IP catalog, called JTAG to AXI Master. Don’t get the two confused.


The Xilinx version is great for issuing TCL commands to address AXI-based peripherals, send and receive data, and verify bus transactions are happening correctly. The MATLAB as AXI Master block provides the same functionality, but instead of TCL in Vivado you can work natively at the MATLAB command prompt.


The hardware I'm using today is Avnet’s UltraZed 3EG System-on-Module. Buy UltraZed 3EG Starter KitBuy UltraZed 3EG Starter Kit


I recently posted Program MiniZed over WiFi using Simulink to introduce a way to quickly start designing Xilinx Zynq SoCs applications, long before you understand the complexity of the hardware and software required. In today’s blog I am narrowing our scope. We’ll put code generation aside and explore a simple way to move samples (data) in and out of the programmable logic (PL) subsystem of a Xilinx MPSoC.


Let’s see how the MATLAB as AXI Master is put into service in a Vivado IPI Block Design for UltraScale+ MPSoC.

I said that the ARM isn’t involved in the system, but here it is in the diagram. Why?


The processor subsystem (PS) is providing the clock to my PL design. That’s all. Nothing else. So the Zynq US+ MPSoC block must be in the design, but rest assured that

no SDK work is required. In fact, the block is automatically configured by way of Avnet's Board Definition File (BDF) for the UltraZed EG kit.


The device under test (DUT) in this case would be any AXI peripheral IP you connect to the master port of the AXI Interconnect block. As a first design, I simply connected an AXI BRAM Controller and a modest amount of BRAM from the Vivado IP catalog.

With this minimal Vivado infrastructure in place, I can now issue simple read/write memory commands in MATLAB to transfer data to/from my IP peripheral (BRAM in this case).


The address of my AXI IP peripheral is easy to find in the Vivado “Address Editor”

You can see the base address of my AXI BRAM peripheral is 0xC000_0000.

To write 255 to my IP peripheral I simply type the following in the MATLAB command window:


     >> h.writememory('c0000000', 255)


To write a block of memory from MATLAB workspace, just reference a variable from your workspace.


     >> h.writememory(' c0000000', pskwave)


Reading from a single location in the peripheral is just as easy.


     >> rx = h.readmemory(' c0000000',256)


If you want to read a contiguous section of memory space in your IP peripheral, specify a start address and offset, and HDL Verifier will retrieve the data.


     >> rx = h.readmemory(' c0000000',32000)


Once you have the data in MATLAB workspace, the signal processing world is your oyster.


You can now run algorithmic scripts to manipulate the data, or use spectral analysis to dissect the frequency domain quality, plot data in a spectrum scope … you get the idea.

Note: you can even program the device directly from the MATLAB command window.


     >> filProgramFPGA('Xilinx Vivado', fpgaFile, 1);


Pretty impressive considering it only requires you to add a small JTAG block into your design. Even a beginner with the Vivado tools can tackle this kind of modification in an afternoon.