Hello all,

 

I wanted to create a post letting everyone know about a new white paper that was generated by one of my colleagues, I have linked it below.  In this white paper, he goes through and describes a design flow that would allow primarily a software engineer to easily work with an FPGA solution that leverages Open-Source C code to produce a Fast Fourier Transform (FFT).  Utilizing the Avnet SOM strategy would allow someone that is not as hardware oriented to be able to produce a highly efficient and customized workable solution.  While an FFT is used in this case, the process is generally the same for including just about any C callable IP!

 

Why would you want to do this, instead of just operating the code as is?

If you are NOT familiar with the FPGA architecture, they are wonderfully capable at processing data and doing it FAST!  Through being able to leverage the parallel capabilities of an FPGA, there are many cases where instead of a LOOP in a LOOP (in a loop...) to process arrays of data, the FPGA might just process all elements at the same time.  It is a higher resolution version of having more processing cores in your computer.

 

If you ARE familiar with FPGAs, still, why would you want to do this?

In my previous life as an FPGA Design Engineer, my main task was to take tested C code that solved a problem and translate that into FPGA VHDL.  It sounds simple, right?  I've left out the few hundred mini-tasks that are involved in that!  I know that creating a board interface solution from scratch might take a month or so, depending on the size of the FPGA and complexity of the devices the FPGA interfaces with.  However, working that ONE important algorithm that was the secret sauce that made our company money, might take 1 month or more, just to get that translated.

 

To reduce this, as mentioned, specialists would create these algorithms - typically simulating in C or C++ under Linux environments.  The algorithms would use data acquired from a signal processing program.  While this was generally fast, the translation and testing in the FPGA itself would take time.  Xilinx's Software Defined System on Chip tool (referred to as SDSoC) allows you to work within a solution space and that tool will manage most of the process for you.  This assumes you have given the tools enough direction to know how to work the solution for you.  Generally, if you leverage an existing SOM or reference design, a platform, or instructions to create one will be or should be provided by the manufacturer.  This is a commitment that Avnet has for the SOM boards that we design and we have started with the SOM products that are most capable related to SDSoC for one reason or another.  We hope to continue building a greater repository with SDSoC Platforms for all of our SOMs!

 

Why would you want to do this, instead of utilizing IP provided by Xilinx?

This is being posted in the FPGA group, so we all know how to use built in IP, right?

As stated above, you might not have TIME to learn how to create an FPGA solution from scratch.  In fact, the white paper actually does compare and contrast built in IP vs SDSoC IP based on the Open-Source C implementation.  The other thing to consider is that your IP might NOT be an FFT, but some combination of a signal processing chain, which might have a CUSTOM CFIR, FFT, data multiplexers or other things that while are not impossible to create, might be limited by the time-frame you need to work in, IP output style (there are a HOST of Turbo Code styles and not all are always supported), or might need a customization that is just not available (number of bits available or some input limitation).  Keep in mind, you will also need to work through all the constraint configurations, clocking configurations, etc.

 

While this is not terribly challenging, it does take time and you need to be accurate with the effort.  You can of course just create a major clock group, or false path everything and the tool will be happy to tell you that you met timing.  The tool only can work within the bounds you provide!  Just as some people just do not have the appropriate skills to layout a Printed Circuit Board (PCB), not everyone has the skills to create an FPGA solution from scratch.  This white paper is a window into the direction Xilinx has taken to open up the power of FPGA processing to the rest of us that just do not have the time to learn how to work through an FPGA solution directly or just do not have the desire to.

 

SDSoC SpeedWay Training

For those unfamiliar with Xilinx SDSoC, one great example of the capability of the FPGA can be seen in one of our training courses, called SpeedWays.  In this FREE of Charge SDSoC centric course, leveraging our MiniZed product, we actually teach you how to create a platform for the MIniZed - from scratch!  This same flow can be used for just about any Xilinx based SoC!  Within this course, you also see a Matrix Multiply example.  You will actually run this example in the SDSoC solution space and see for yourself that an FPGA running at slower than 1/10 the clock rate of an ARM processor - running standalone, no interference from Operating System interrupts, etc. - is easily capable of ~15x performance gains.  This is utilizing default settings!  The course does not go into too many more details, but provides a host of links to other documentation to enable you to learn more.  One of Avnet's specialists was actually able to tweak a few settings and was able to demonstrate the solution running closer to 30x improvement!

 

Not familiar with MiniZed, Vivado or the Xilinx SDK?

We have you covered!  With three other courses available, we can give you the skills you will need to be able to work with SDSoC.  The Software and Hardware SpeedWays are considered prerequisites to the SDSoC SpeedWay.

 

For access to this white paper:

Navigate to Avnet's SOM support site Zedboard.org

Then click through Support → Reference Design / Tutorials → UltraZed-EG IO Carrier Card

Or click this link | Zedboard  | to directly enter the proper reference design section.

Look for "SDSoC C-Callable FFT IP White Paper" and click the Download button.  As of this blog, there are versions for 2017.4 and 2018.2.  Please note that there were significant changes in the tool and flow between those versions.  Choose the proper white paper to follow along with your own tools!

 

For access to the SpeedWays:

Navigate to the Zedboard.org site, and login.

Then click through Support → Training and Videos

Or click this link Training and Videos | Zedboard  to directly enter the proper Training section.

Listed in the order that we recommend you take these courses, are the SpeedWay training materials.  They are listed under the "MiniZed Speedway Design Workshops" heading.

While the "Integrating Sensors on MIniZed with PetaLinux" is not required for SDSoC, it can be valuable if you intend to run PetaLinux on your SOM!

 

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