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The Universal DELAY Building Block  This is the first post in this blog in which I will try to actually design something useful based on the ideas introduced so far. Also, instead of just short code snippets, the code examples in this post are complete and they can be simulated, synthesized and used in actual designs.   We will try to create a generic and reusable delay module - the goal is to delay a signal of some given type by a fixed but arbitrary number of clocks, this is a fund ...
We're Not in Kansas Anymore  In this post we will try to do things you probably never tried to do using VHDL, assuming they were not even possible in such a low level language.   VHDL and Verilog/SystemVerilog are considered low level hardware design languages, compared with C/C++ based HLS flows for example. Only schematic capture is lower on the totem pole and hopefully nobody is still doing FPGA designs using schematics anymore. But the low level label attached to HDLs is only par ...
VHDL User Defined TypesNUMERIC_STD SIGNED is not a good choice for fixed point arithmetic  Most signal processing applications require handling fixed point data types, not just integers. These numbers have a binary point, assuming we use binary or base 2 representation, with an integer part to the left of the binary point and a fractional part to the right of it. While it is possible to use integer numbers for that with an implicit binary point position there are numerous problems when try ...
Beyond STD_LOGIC  In the last post we just started to scratch the surface of VHDL types. This time we will try to go deeper - which types should we use, what are their properties and limitations, what are the main pitfalls a beginner would encounter and how to solve them.   We have seen that while the basic type for software programming is INTEGER, of various but fixed sizes, signed or unsigned, the VHDL fundamental type is the 1-bit STD_LOGIC. It has 9 possible values, some of which ...

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