Introduction

They may seem like an unlikely or odd couple: art and technology. Art implies the vast realm of unbridled creativity, while technology is bounded by empiricism: rules, standards and rationality. But when art and technology are interwoven, new vistas are revealed, new ideas are born, and new technologies with a distinctive twist are realized. In his Art of FPGA Design Series, Xilinx employee and designer Catalin Baetoniu breathes life into the finer points of designing with FPGAs. Enjoy.

 

The Carry-Save Adder, Two for the Price of One

When developing software the CPU and memory your code is running on is already paid for and there is little incentive to optimize your code to make it either smaller or faster. But as a hardware designer you literally pay for every LUT and FF in the FPGA you are using. If you could make your design smaller and faster you could do more with the same FPGA or you could use a smaller and cheaper one and if your volume production is significant this can translate into a lot of money. Fabric adders are one such good opportunity to increase the efficiency of a hardware design.

 

Counters, Adders and Accumulators

One of the most common operation encountered in digital hardware design, especially for digital signal processing applications, is addition. This actually covers a large group of fundamental building blocks, like up/down binary counters, adders/subtractors, comparators, accumulators and so on. (Oct 16 2018)

 

The Universal MUX Building Block Part 3

We have seen in the previous post that Vivado Synthesis is able to optimally infer a mux form behavioral code for multiplexers with up to 16 inputs, but beyond that not so much. The synthesis results are not bad but for high performance designs where every LUT and especially every logic level counts not bad is not good enough. (Oct 9 2018)

 

The Universal MUX Building Block Part 2

So the question is now what is the most efficient implementation for arbitrary size multiplexers one should expect? If the result the synthesis tools infers from behavioral code is equal or very close to this there is no need for a specialized MUX Building Block. If the difference is significant then there will be a definite need for such a block, especially for designs with large muxes and/or many of them. (Oct 2 2018)

 

The Universal MUX Building Block

The next example in the series of generic building blocks is a multiplexer. This is a combinatorial block - if we need pipelining we can always add that separately to keep it as generic as possible - with an input port I of N elements, an UNSIGNED SEL port and an output port O, which is one of the N elements of the input port I selected by SEL. We want of course the I and SEL ports to be unconstrained arrays. (Sept 25 2018)

 

Instantiating LUT6 Primitives Part 2

Today I will show a couple of examples where LUT6 primitive instantiations make sense. To keep things short and simple these are somewhat artificial examples but situations like these tend to show up all the time in hardware designs. Let's say we need a 48-input AND function. This can be coded very easily behaviorally, especially if we take advantage of the new VHDL-2008 features. (Sept 18 2018)

 

The Art of FPGA Design: Instantiating LUT6 Primitives Part 1

In the previous post we have already seen how to instantiate FPGA primitives, SRL16s in that case. The role of the synthesis tool is to take HDL behavioral code and translate it into a netlist of FPGA fundamental building blocks called primitives. This is very much like the software design flow, where a C compiler takes C code and produces machine code that a processor can execute. (Sept 11 2018)

 

The Art of FPGA Design: The Universal DELAY Building Block Part 2

In the last post I have introduced an example of a universal delay block that uses a behavioral implementation to create a reusable module that can be used to delay a signal by an arbitrary but fixed value. Both the delay size and its width are generic respectively unconstrained, which makes the design reusable. While the behavioral implementation is quite compact and elegant, the synthesis result is not always what we really need. It is left to the synthesis tool to decide how to map our behavioral code into available FPGA primitives. (Sept 4 2018)

 

The Art of FPGA Design: The Universal DELAY Building Block Part 1

This is the first post in this blog in which I will try to actually design something useful based on the ideas introduced so far. Also, instead of just short code snippets, the code examples in this post are complete and they can be simulated, synthesized and used in actual designs. (Aug 28 2018)

 

The Art of FPGA Design: We're Not in Kansas Anymore

In this post we will try to do things you probably never tried to do using VHDL, assuming they were not even possible in such a low level language. VHDL and Verilog/SystemVerilog are considered low level hardware design languages, compared with C/C++ based HLS flows for example. Only schematic capture is lower on the totem pole and hopefully nobody is still doing FPGA designs using schematics anymore. But the low level label attached to HDLs is only partially correct. They are low level only if you use them that way. It is possible to do very high level things in VHDL if you really want. (Aug 21 2018)

 

The Art of FPGA Design: VHDL User Defined Types

Most signal processing applications require handling fixed point data types, not just integers. These numbers have a binary point, assuming we use binary or base 2 representation, with an integer part to the left of the binary point and a fractional part to the right of it. While it is possible to use integer numbers for that with an implicit binary point position there are numerous problems when trying to use the NUMERIC_STD SIGNED type for that. (Aug 14 2018)

 

The Art of FPGA Design: Beyond STD_LOGIC

In the last post we just started to scratch the surface of VHDL types. This time we will try to go deeper - which types should we use, what are their properties and limitations, what are the main pitfalls a beginner would encounter and how to solve them. (Aug 7 2018)

 

The Art of FPGA Design: What's Your Type?

People new to VHDL usually come from a software background, maybe C/C++ or Java and might have a difficult time grasping the fundamental concepts of HDLs. VHDL in particular can be used as a sequential software language - everything you can do in C you can do in VHDL and while this might make sense when creating testbenches for functional simulation it is not the right approach for actual hardware design. (July 31 2018)

 

The Art of FPGA Design: Two Free VHDL Books

If you installed Vivado WebPACK, the free version of Xilinx FPGA design tools, you are ready now to start creating your first hardware design. There are at least three different ways to program a Xilinx FPGA today, using a hardware description language like VHDL or Verilog/SystemVerilog, using Vivado HLS using C/C++ and Vivado SystemGenerator or ModelComposer which requires Matlab and Simulink. Each design flow has advantages and disadvantages and the third one is not free. (July 24 2018)

 

The Art of FPGA Design: Why learn FPGA Design?

I have been asked in the comments why invest time and money to learn how to use FPGAs? First of all, if you are interested in advanced digital hardware design FPGAs are essentially the only game in town. Unless you are working on million dollar ASIC designs, the only way to do really advanced hardware design at a reasonable cost is with an FPGA. (July 17 2018)

 

The Art of FPGA Design: Why Not Try FPGA Design

Can you do FPGA design or teach yourself the skills required to do that with a $0 budget? Electrical engineers (and hobbyists and students and young - or old for that matter - people interested in electronics) are running out of excuses for not trying to learn FPGA design.