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Sorting Networks   Sorting networks are an interesting and unsolved mathematical puzzle. They are quite different from the usual sorting algorithms one encounters in computer science like bubble sort, quick sort, merge sort, heap sort and so on. While sequential algorithms are generic, in the sense that they work on an input set of items of any size, their execution time grows with N, either as  O(N·log2N) for the fast algorithms or  O(N2) for the more trivial ones and the ...
Here is the new release 0.1a of XXICC.  Rev 0.1a adds the return statement to GCHD (GalaxC for Hardware Design) which allows a hardware module to return a value without using an output port.  Rev 0.1a also adds GCHD comparison operators missing from earlier releases: x < y, x <= y, x > y, and x >= y.  Rev 0.1a also fixes some bugs, mostly involving n-bit integers.   XXICC (21st Century Co-design) is a not-for-profit research project which attempts to bring digit ...
Sorting and Searching Algorithms   Now that we went through a variety of VHDL design building blocks and we saw the techniques to create both generic, reusable and at the same time efficient (in terms of speed and area) designs, using either behavioral inference or primitive instantiations, it is time to put what we have learned in practice. We have already looked briefly at FIRs, Finite Impulse Response Filters in the context of introducing the DSP48 primitive, there is a lot more to be s ...
The DSP58 Primitive   Xilinx has recently announced a new 7nm FPGA family called Versal. Devices in this family will have an improved version of the UltraScale/UltraScale+ DSP48E2 primitive we just studied in the last posts. The new Versal primitive is called DSP58 and there are numerous improvements compared to the earlier DSP48.   First of all, the signed multiplier, which was 27x18 in DSP48 is now 27x24 and the 48-bit post-adder/accumulator is 58 bits, which is where the name of ...
The DSP48 Primitive - Complex multipliers   Traditionally a complex multiplication can be decomposed into four real multiplications and two additions:      x+i·y=(a+i·b)(c+i·s)=(a·c−b·s)+i·(a·s+b·c) where     i=√−1   This maps well into four DSP48s, including the two additions, which can use the post-adders and the DSP48 P cascades. The latency of a fully pipelined DSP48 implementation is fo ...

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