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Tic-Tac-Toe is one of the best known games in the world. A group of students port Tic Tac Toe to Digilent Arty A7 Field Programmable Gate Array (FPGA) platform.  The game uses the classical Tic Tac Toe grid of 9 squares, running on a VGA monitor using a 640x480 resolution. Players can use a PS/2 keyboard as the game controller. Pressing up, down, left and right select a square on the game board and hitting “ENTER” or “SPACE”  place the square on the board. A pla ...
I'm going to borrow heavily from my colleague Tom Curran and his excellent HDL howto blog (Avnet HDL git HOWTO (Vivado 2020.1 and earlier)). I highly recommend reading through that blog before continuing. I will modify it as needed to help you build the hardware design for the 96Boards ON Semiconductor Dual Camera Mezzanine design using Ultra96-V2. I will preface this blog post by saying I have been a power and hardware designer most of my career. In an effort to diversify and help out on more p ...
Xilinx Vitis 2020.2 Edge Acceleration on Hackster.io Developing accelerated applications using the Xilinx Vitis tools may be straightforward, but the installation process can be daunting. This project aims to help new users clear the initial hurdle of getting the Vitis tools installed to target the Xilinx ZCU102 development board. I wrote a short article on Hackster.io to show an installation process with the least number of steps. The instructions are short partly because PetaLinux is not requi ...
The Single Rate Half-Band FIR   We have started by looking at the most general version of an FIR filter. From a mathematical point of view, this is all that is needed. There are countless variations, like the symmetric versions, both odd and even, they are just particular cases of the general FIR algorithm and they present little interest to a mathematician. But from an implementation point of view, these particular filter versions do matter. One such example is the half-band FIR, which wi ...
As you may already know, the Avnet Ultra96-V2 single board computer does not have a wired Ethernet port on the board.  That means if we want higher Ethernet data throughput than the on-board WiFi can provide we need to go exploring for options.  I recently wrote about Enabling USB Gadget Ethernet on the Ultra96-V2 as a way to accomplish this.   But what if we need even higher Ethernet throughput than USB gadget Ethernet can provide?  Thankfully the Ultra96 board is very vers ...
This project details how to build a stereo depth camera with AI capabilities on a ZYNQ MPSOC platform.   This time we'll see how to use the Vitis Vison layer L1 libraries and PYNQ framework to implement a complete stereo depth pipeline. There are a number of past and existing bugs on Vitis Vision libraries so this procedure has not been smooth. In addition the PYNQ framework is in a state of flux (from 2.5.1 to 2.6) so there are some API changes.   1. Setting up the environment Fi ...
The Single Rate symmetric FIR, low latency transposed architecture   The question we need to answer now is this - for those applications that require very low latency FIRs is there a way to avoid the increase in latency proportional to the filter order that is characteristic of direct systolic implementations, both non-symmetric and even/odd-symmetric ones? We have already seen in Post 5 that the answer to this question for the non-symmetric FIR case was yes. By using the transposed FIR i ...
Hi all,   I was working through some interesting designs on Vitis recently and a colleague of mine brought up a great question. "What are the actual Vivado implementation settings for the different Vitis --optimize switches?"   Not sure what Vitis is?  Check out my other blog series on Vitis to get an idea.  If that doesn't help you, you can checkout my webinar I did.  That webinar will start building up your skills from the ground up as well as point you to a few rea ...
The Single Rate odd-symmetric FIR   In the last post we have examined the even-symmetric FIR, a filter of order N=2*K. The main conclusion was that we only need K DSP48s to implement such a filter, and we came up with a basic building block that is both efficient in terms of device utilization, generic and scalable. We can build filters of virtually any size simply by cascading this block, with no speed degradation as the filter gets larger.   We will now consider the odd case, whe ...

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