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Multichannel  and Overclocking FIRs - The Single Rate Symmetric Case   In the last post I created an overclocked or semi-parallel implementation of a systolic, non-symmetric FIR, where each DSP48 in the chain implements M taps of the filter. The filter sample rate is M times slower than the system clock rate, but the device utilization is also M times smaller, N/M DSP48s instead of the normal N, where N is the filter order.   Many times the FIR filter is symmetric and the DSP4 ...
Interested in implemented AI at the edge with the Avnet platforms ?   Check out my new designs for Vitis-AI 1.3, the latest edge AI solution for Xilinx based platforms.   Vitis-AI 1.3 flow for Avnet Vitis platforms This project provides detailed instructions for targeting the Xilinx Vitis-AI 1.3 flow to the following Avnet Vitis 2020.2 platforms: Ultra96-V2 Development Board UltraZed-EV SOM (7EV) + FMC Carrier Card UltraZed-EG SOM (3EG) + IO Carrier Card     Vitis-AI ...
We've talked in this blog space and elsewhere about testing WiFi performance for the Ultra96-V2 board on a LAN using iperf3.  It is a very handy and useful test, but it only tests local (WLAN) throughput.  What about if you are developing an IoT product and your Ultra96-V2 needs to communicate with other devices or cloud services over the internet?  How do you test WiFi performance over the internet to the Ultra96-V2 board if you need to rely on command line access (no mouse, keyb ...
Multichannel  and Overclocking FIRs - The Single Rate non-Symmetric Case   We are looking now at the case of the single rate FIR filter where the sample rate is a sub-multiple of the FPGA clock rate. For example, let's say that the input and output sample rates of our single rate FIR of order N=8 are 200Msps, but we know we can run our FPGA DSP48s and fabric at 800MHz. We can take advantage of the extra FPGA speed in two ways. We can either implement four such filters for the price o ...
Taking advantage of coefficient symmetry in Polyphase FIRs   We have seen in previous posts that when the FIR coefficients are symmetric, we can use a DSP48 feature called a pre-adder and reduce the number of multipliers required in half. Essentially, an FIR of order N can be implemented with N/2 DSP48s.Taking advantage of the filter symmetry is important, especially when the FIR is large or there are many instances of such filters in a design. The DSP48s are a scarce resource and reducin ...

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