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June 2021 Next month
The goal of this blog series is to master the Xilinx Zynq. I'm using the PWM design of my previous posts, and now switch to the raw AXI memory map interface between ARM and FPGA. In the previous post, I used AXI GPIO, the first step to memory mapped interface between the Linux and FPGA parts. Now I'm using the pure memory map (MMIO).   There isn't a lot of difference between the previous blog and this one. In fact, the previous one was a little but easier to use. But this one is our st ...
I posted a series of FPGA blogs. They focus on the toolchains and steps to get a working design. A common theme in those articles is the VHDL source. Each time, it's a PWM generator. A specific kind of PWM block: it can generate complementary output signals, to drive a transistor half bridge.   In this post, I'm drilling into that VHDL part.     Why this PWM module with 2 outputs and dead time I wanted to use a relevant exercise that solves a common task in electronics: driv ...
The goal of this blog series is to master the Xilinx Zynq. I'm using the PWM design of my previous post and switch to AXI memory map interface between ARM and FPGA. I learned this from beacon_dave 's PYNQ-Z2 Workshop - AXI GPIO post.   ARM/Linux to FPGA interface: from GPIO to AXI memory mapped register  in the previous post, I made a PWM generator in VHDL for the Zynq. I used the ARM EMIO GPIO bus as the interface between ARM and FPGA fabric. This is a 64 bit bus. I used 8 bits ...
The goal of this blog series is to master the Xilinx Zynq. I'll try to build a PWM controller for a half bridge power design. I've made a PWM with dead time design for the Xilinx Spartan 6 FPGA in 2017. I'm now learning to design for Zynq (I got a Pynq-Z2 board from our balearicdynamics!). I use the 2017 Spartan 6 design as a starting point.     Goals for this post  I want to have that PWM VHDL design running on the Zynq, and be able to change the dead time and duty cycle fro ...

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