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michaelkellett

Cheap Cyclone 10

Posted by michaelkellett Top Member Jul 31, 2021
I've been following the discussions about the VIDOR4000 in the FPGA group. There was a giveaway associated with the Webinar but of course there will be sonme disapointed non-winners.   If you want to get into playing with FPGAs one of the cheapest routes I've found so far is to buy a simple dev board from Aliexpress. There are lots avaialble but this blog is about the Cyclone 10 board from QMTech. https://www.aliexpress.com/item/1000006634063.html?gps-id=pcStoreJustForYou&scm=1007.23 ...
Have you heard about Xilinx’s latest release in the 16nm line, the ZU1/2/3 InFO package? This package uses 60% less area and is roughly 70% thinner than standard Zynq UltraScale+ chip. InFO (for those that don’t know) stands for Integrated Fan-Out. This technology was developed by TSMC and expands on Fan-out wafer-level packaging. To sum up how this is done compared to previous packaging technology, the InFO silicon dies have their packaging grown into them instead of being diced up ...
Introduction   Now a little project: a servo interface. This will give me a chance to experiment with some very simple communication between the microcontroller and the FPGA on my VIDOR 4000 board.     I'm going to have 8 servo channels, which the FPGA will drive out on the D0 to D7 pins of the header, and the control will be via a simple, write-only SPI interface on the SCK and MOSI pins from the SAM processor [with A0 used as the SS chip select].   I'm sure, if I looke ...
jc2048

VIDOR 4000: Clock Jitter

Posted by jc2048 Jul 12, 2021
Without connecting anything else to the VIDOR, the only clock we're given to work with is one that comes from the SAM microcontroller. Here it is on the VIDOR schematic, output from the SAM part and going into one of the dedicated clock inputs.         I haven't tried to look at it directly with the 'scope. The processor is in quite a confined space between the headers, so it would need doing very carefully.   If I take that clock and simply push it back out ...
Introduction   In this blog Add Pynq-Z2 board to Vivado Jan refers to a Johnson counter. I struggled to remember what a Johnson counter actually was, but, for some reason, the number 4017 came to mind. Sure enough, the CD4017 CMOS logic device turned out to be a decade counter/decoder implemented as a 5-bit Johnson counter with ten output decodes. The datasheet [1] even had an equivalent circuit for me to look at.     I also found a description of the counter in Designing with ...
DIY Test Instrumentation        Submit an EntrySubmit an Entry  Monthly Themes  | Monthly Poll  |  Back to homepage   This DIY instrument is a PWM generator with dead band support. It has 2 complementary outputs and supports dead time. It can safely drive a (GaN) half bridge.     Specifications  PWM with fixed frequency: 1.5625 MHz Duty cycle: 6 bits (64 steps) Dead band: 0 - 150 ns, 4 bits (16 steps of 10 ns) ...
The next step in my Zynq and Pynq learning; get information from an FPGA design into the Linux part: a rotary decoder that can read the movement of a scroll wheel. The original blog post for Spartan 6 and Xilinx ISE Webpack: Rotary Encoders - Part 5: Capturing Input on an FPGA   In this design, the FPGA decodes movements of a rotary encoder. The value is then written to a memory mapped register, that can be read from the Linux side. I will read it from a Jupyter notebook.   ima ...

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