Skip navigation
This post is a follow up on a previous article to generate a quadrature clock for shabaz 's Software Defined Radio (SDR) Experiment Board. It's a circuit with 4 PWM outputs that are each 90° shifted. I'm adding programmable frequency control. Without the need to change the fabric clocks. It will be a VHDL module, that's put in between the fabric clock and the quadrature oscillator from the previous blog. A register allows you to control the output frequency.     Programmable ...
Introduction Workshop 4 of the Summer of FPGA series for the Ultra96-V2 board went through a design for using the Mezzanine Click board.  It was covered 'at pace' and this blog is my jottings on the steps taken, specifically elaborating on some of them with more information.  Really, I'm providing them for others to get some of the insights I gained whilst re-creating the design from scratch.   You should watch the Video associated with this workshop and read this blog in tandem ...
Introduction Workshop 4 of the Summer of FPGA series for the Ultra96-V2 board went through a design for using the Mezzanine Click board.  It was covered 'at pace' and this blog is my jottings on the steps taken, specifically elaborating on creating and using a PWM custom IP.  The video covered how to do an initial creation of a new IP but then copied pre-made files to provide the implementation.  I wanted to understand how this process would work from scratch: please bear in mind ...
Hello!   Looking for a new Xilinx SBC to play with or the best Xilinx Zynq or Zynq UltraScale+ SOM to use in your product?  Can't decide what Avnet SOM or SBC is the best fit for your application?  Avnet has just published a new Xilinx Solutions Guide:   Avnet Boards Xilinx Solutions Guide   Inside you will find 24 pages of product selector guides, product info, block diagrams, accessories, and information on our other related products and services to accelerate your ...
When you're working on a Vivado Block design, you can add IP. There are 100s of options available. But you will not find a NOT gate, AND gate, ... They are there though, available under the cryptical name Utility Vector Logic and Utility Reduced Logic     Utility Vector Logic: Works on vector inputs, and outputs a vector where the logic has been applied to each of the bits. There is AND, OR, XOR and NOT   Utility Reduced Logic: Here, the inputs are also vectors, but the resul ...
Introduction: Back then in February when I roadtested the USB104-A7, I had learned to create block designs using MicroBlaze. I found it very interesting but the available online resources were limited, the tutorials were based on the older versions of Vivado (Uploaded 6 years back or so). So I thought of making a course on using MicroBlaze in block designs and programming it with Xilinx SDK. Finally, after my semester exams were over, I got some free time to record the tutorials and the course ...
Read this for info only. The project doesn't work.   There is an example project that shows how to run OpenCV functions in FPGA instead of on a processor. This practice of off-loading heavy processing from software in the processor to hardware designs running inside the FPGA  fabric is called hardware acceleration. I reviewed it here: Learning Xilinx Zynq: Hardware Accelerated Software. In this series, I will try to do the same, with the 2020.2 toolchain and sources.   Part 2 ...
Read this for info only. The project doesn't work.   There is an example project that shows how to run OpenCV functions in FPGA instead of on a processor. This practice of off-loading heavy processing from software in the processor to hardware designs running inside the FPGA  fabric is called hardware acceleration. I reviewed it here: Learning Xilinx Zynq: Hardware Accelerated Software. In this post, I will try to do the same, with the 2020.2 toolchain and sources.   Vitis HL ...
Life hack to automate the creation of a project in Vivado.   video source: real time capture of script execution on my laptop   Many projects have repeatable steps at the setup stage. This script helps to automate this. It creates a new project with your typical starting blocks. Before calling the script, close the currect project, if one is open. If you just opened Vivado, you are good to go. The Tcl prompt is at the bottom of the startup screen. Set these two properties using ...
The main target for Zynq family FPGAs is: compute systems with hardware acceleration. It's architecture focuses on being able to stream data efficiently between ARM and FPGA submodules. The FPGA can then perform manipulations in hardware that take too long in software. The tool chain supports this. The Vitis HLS IDE's only goal is to convert C functions to FPGA IPs..   Hardware Accelerated Image Resize Algorithm  As proof of concept,  Xilinx adapted OpenCV so that you can buil ...
shabaz made a Software Defined Radio (SDR) Experiment Board. One of the components is a digital quadrature oscillator. It's a circuit with 4 PWM outputs that are each 90° shifted. In Shabaz' blog, the oscillator is made with flip-flops, and controlled by an external function generator. Because it's the Summer of FPGAs, I'm proposing 2 FPGA based alternatives. They work identical, generate the same frequency (input / 4), but the approach is different. One works by replaying a predefin ...
Store 1024 12 bit values in a VHDL RAM design, and automatically test it.   This post uses the VHDL RAM design of Michael Kellett on a Zynq. You can store data and read it back. The design was done out of curiousity. To see how and when Block RAM slices are used. Check the discussions in the comments of MKs post. Here, I just focus on how the exercise is done with Vivado, Zynq and Pynq. If this blog proves anything, it's that HDL is very portable.   VHDL Memory component  VHD ...
Every FPGA and Programmable Logic SoC development board has the ability to plug in add-on boards to expand the functionality of the basic board. When you are deciding on which board to use for your own learning or proof-of-concept, it's important to consider if you will be easily able to add on the additional circuitry that you need for a complete system.   My purpose with this blog is to discuss 6 different expansion standards that I've seen on these various boards and where you can get m ...

Filter Blog

By date: By tag: