This post is a follow up on a previous article to generate a quadrature clock for shabaz 's Software Defined Radio (SDR) Experiment Board.

It's a circuit with 4 PWM outputs that are each 90° shifted.

I'm adding programmable frequency control. Without the need to change the fabric clocks.

It will be a VHDL module, that's put in between the fabric clock and the quadrature oscillator from the previous blog. A register allows you to control the output frequency.



Programmable Frequency


There are several options to generate a variable frequency with an FPGA:

  • Use a std_logic_vector counter incremented at the input clock, and select what bit you'll use as output clock. The LSB will generate the fastest clock, MSB the slowest (examples).

  • Use a counter that indicates how many input clock ticks you wait before toggling the output clock. I'm writing one of these in this post.
  • clock wizards and proprietary IP that offer PLL and other device specific precise derived clock signals.


Here's the VHDL code. I attempted to make it easy to read. No tricks or smart things. Critique and advice: put it in the comments.



source available as GitHub Gist.


library IEEE;

entity variable_clock is
    Port ( 
      clk_i    : in  STD_LOGIC;
      resetn_i : in  STD_LOGIC;
      ticks_i  : in  STD_LOGIC_VECTOR (7 downto 0);
      clk_o    : out STD_LOGIC
end variable_clock;

architecture Behavioral of variable_clock is
  signal s_counter: natural range 0 to 2**ticks_i'length-1 := 0;
  signal s_clk_out: STD_LOGIC := '0';

process (clk_i, resetn_i)
  if resetn_i = '0' then
    s_counter <= 0;
    s_clk_out <= '0';
  elsif rising_edge(clk_i) then
    if s_counter >= unsigned(ticks_i) then -- >= because the value can change
      s_counter <= 0;
      s_clk_out <= not s_clk_out;
      s_counter <= s_counter + 1;
    end if;
    clk_o <= s_clk_out;
  end if;
end process;

end Behavioral;


You can set the program register between 0 and 255.

A full output cycle requires two toggles of the output signal. A toggle to generate the high halve of the period, a second one to generate the low halve.

By incrementing the program register, you add the time of one input clock tick to each half period of the output.


If you put it to 0, it will toggle the output at each rising edge of the input clock.  It requires two input clock ticks for a full period so it halves the input clock frequency.

If you pass 1, the block will ignore 1 input clock tick before toggling the output. 4 input ticks are needed to generate one output clock period.

If you pass 2, 2 ticks are ignored at each output toggle. It takes 6 input ticks to generate a full period.


In my example, I'm driving the input with a 100 MHz fabric clock.

One period is 10 ns. So we get a rising edge each 10 ns.

Because we add 2 input ticks for each increment, the output period gets 20 ns longer each time.

Let's see what the results is:


register valueoutput clock periodoutput clock frequency
02 * 10 ns = 20 ns1/20 ns = 50 MHz
14 * 10 ns = 40 ns1/40 ns = 25 MHz
26 * 10 ns = 60 ns1/60 ns = 16.667 MHz


The formula: (register value + 1) * 2 * input clock period = output clock period.


video: a Jupyter notebook sweeps through the frequency range


Fit it into the Quadrature Oscillator design


The purpose of this variable frequency block is to  control the speed of the quadrature oscillator of the previous post. This is an easy exercise, done in Vivado.

Remove the link between fabric clock and quadrature oscillator clock input.

Add your new variable clock IP to the design by adding it to the block diagram. Link its clock input to the fabric clock. Clock output to the quadrature oscillator.

I've exposed the variable clock output so that you can probe it and verify the claims above. This is optional.



The reset is shared with the rest of the PL.

The ticks_i register is an 8 bit input.

In my design, I've attached it to the ARM/Linux part via the AXI interface. That makes that I can program it from the ARM/Linux part.



This is a choice specific to achieve my goal of having it software changeable. You could also control it from an FPGA quadrature decoder block, from 8 input pins, an FPGA sweep generator (counter), ...


Jupyter notebook


The notebook allows you to load the bitstream into the FPGA, and set the register of the variable clock:


The Vivado project is attached to this post.


I used a hierarchy to show the variable clock and the quadrature oscillator as one block on the main design:

the content of the dark blue block is the 1st image at the top of this article.



Pynq - Zync - Vivado series
Add Pynq-Z2 board to Vivado
Learning Xilinx Zynq: port a Spartan 6 PWM example to Pynq
Learning Xilinx Zynq: use AXI with a VHDL example in Pynq
VHDL PWM generator with dead time: the design
Learning Xilinx Zynq: use AXI and MMIO with a VHDL example in Pynq
Learning Xilinx Zynq: port Rotary Decoder from Spartan 6 to Vivado and PYNQ
Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control
Learning Xilinx Zynq: use RAM design for Altera Cyclone on Vivado and PYNQ
Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations
Learning Xilinx Zynq: a Quadrature Oscillator - variable frequency
Learning Xilinx Zynq: Hardware Accelerated Software
Automate Repeatable Steps in Vivado
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 2: Vivado Block Design
Learning Xilinx Zynq: Logic Gates in Vivado
Learning Xilinx Zynq: Interrupt ARM from FPGA fabric
Learning Xilinx Zynq: reuse and combine components to build a multiplexer