Having used Vivado as a hobbyist for several years now I feel more confident in tackling the inevitable errors, but still often get stuck. Therefore to help others, and my forgetful self in coming months, I thought a quick blog post may be useful. I know from my own learning that similar sources have been invaluable to overcoming errors and mistakes in my designs.

 

I jumped into the deep-end of the FPGA world and almost immediately started using the complex IP blocks for great functionality. More recently I've taken a few steps back and I'm currently experimenting with RTL blocks and Verilog. My aim is being to be able to create my own complex and bespoke IP blocks. Most of my experimental projects have been successful, writing simple RTL modules, adding them to a block diagram, setting up the constraints file, simulating and finally downloading the bitstream and proving the design on the hardware.  Today my RTL and Verilog tests have been based on the familiar half-adder block:

Which then failed...

I spent a while looking through the Verilog code, made a few adjustments, changed a few port names to make the error more obvious (i.e. both half and full adders had 'sum' and 'carry' ports) but the error remained fairly consistent throughout.

 

Then I noticed the sources window looked different to the usual layout. The wrapper was normally at the top and instead my FullAdder was appearing there. A right-click on the design wrapper allowed me to select that at 'top' and for me, and this cured the errors.

I'm unsure how I messed that up. I had made a block diagram and selected 'create HDL wrapper' - maybe I'd somehow dragged and dropped afterwards? Maybe I clicked the wrong item? Next time I'll be a bit more careful. Anyway, hopefully this blog will prove useful to others with a similar error in that they can ensure this is not the cause of their errors.