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2 Posts authored by: bhfletcher element14 Team
Note: The v1.0 Ultra96 board definition files (BDF) embedded in Vivado 2018.1 and 2018.2 have a bug. The latest BDF is on the Avnet GitHub here: . The article below describes the parameters included in the v1.2 board definition file.   The Avnet Ultra96 board from Avnet has 2 GB of LPDDR4 RAM that is interfaced to the Zynq UltraScale+ MPSoC's Processing System (PS) DDR Controller. This versatile controller is described in Chapter 17 of the ZU+ Technical Referen ...
Question: How did Avnet arrive at the DDR Delay values published in the MiniZed board definition file?   That's a good question! We developed the MiniZed board definition file with Vivado 2016.4. The settings you will find in the Avnet MiniZed board definition/awareness preset.xml are: Calculating these requires you to know the routing length in millimeters for the DDR clocks, DQS, and DQ traces. For MiniZed, we publish this in the net length report. You need clock and strobe for each 8 bi ...

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