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11 Posts authored by: bhfletcher element14 Team
I previously wrote about Board Definitions in this blog: How to Leverage Board Presets to Accelerate Your Vivado Design   That blog discussed creating your own Board Repo to add Board Definitions. Vivado has a built-in way to do this graphically, pulling the Board Definitions from a resource called the Xilinx Board Store. The purpose of this blog is to show an alternative way to add Board Definitions to Vivado. It is not intended that you do them both, so pick which method you prefer!  ...
Note: This is one alternative for adding board definitions to the Xilinx tools the other option is documented here. Xilinx BoardStore to Automate Vivado Board Definitions for Avnet Boards   For anyone just getting started with Xilinx Vivado, a good place to start is UG895 Vivado Design Suite User GuideSystem-Level Design Entry https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug895-vivado-system-level-design-entry.pdf   It is 128 pages long, and sometimes it's eas ...
If you have ever wanted to experiment with a Xilinx FPGA, here’s a chance to get a Spartan-7 version for free, along with an ST Micro PmodNAV! Winners Announced: We're Giving Away Up to 10 Arty-S7 Boards to Use in an Upcoming Xilinx Workshop!   If you don’t get a free one, the Arty-S7-50 has been marked down to $109 for this event. You can purchase the Arty-S7 and PmodNAV at the links below. Buy Arty-S7 with XC7S50 Buy ST Micro PmodNAV   This goes along with a hands-on ...
Last year when Avnet released the Technical Training Courses for Ultra96, the courses were based on Xilinx 2018.3 tools, which did not include Xilinx Vitis. This 2018.3 Ultra96 TTC Series includes 8 total days of training across 6 different introductory and advanced courses, which is great! The courses do cost a small amount of money, but for the quality/quantity of training, it is a really incredible deal and still well worth the money and effort. Unfortunately, based on the timing of the devel ...
Within the Avnet 'Zed' Community, we spend a lot of time talking about SoC's with hard-core processors. The original ZedBoard started it all with a Zynq-7000 device with ARM A9. We've also done a lot with Zynq UltraScale+ family and ARM A53 (UltraZed, Ultra96). However, what if you don't need the ARM? What if Microblaze is good enough or you don't need a processor at all?   If you are looking for a more traditional, PL-only device, then Spartan-7 may be a good, low-cost choice. If you don' ...
Avnet has partnered with Adam Taylor to offer three FREE days of training to help you get started with Xilinx Embedded Design! These trainings include a mix of recorded lectures and hands-on labs with the Avnet MiniZed Development Board. The trainings are targeted at new users, so if you've wondered where to begin, this is the place!     The trainings are based on the Xilinx 2019.1 tools. We are aware that 2019.2 is now out, including Vitis. Hopefully we will update the trainings in ...
On Feb 18th, 2020, Avnet announced the availability of an Industrial-temperature grade Ultra96-V2. https:/
ews.avnet.com/press-release/avnet/avnet-upgrades-ultra96-v2-single-board-computer-industrial-temperature   This was something we hinted at last year when Ultra96-V2 was first released. This was mentioned again in ctammann's blog that discussed a new heatsink design for Ultra96-V2: Thermal relief is critical - design example around Ultra96-V2   I wanted to share a few more det ...
The Xilinx Zynq UltraScale+ MPSoC device has an integrated Platform Management Unit or PMU. This PMU's functionality is described in Chapter 6 of Xilinx UG1085, Zynq UltraScale+ Device Technical Reference Manual. The PMU controls many things on the ZU+ device, including powering up and down the ZU+. The Ultra96-V2 incorporates an On/Off controller to interface between the on-board power regulators and the ZU+. This allows the ZU+, Power Button, and regulators to seamlessly work together to power ...
bhfletcher

Introducing Ultra96-V2

Posted by bhfletcher element14 Team Mar 28, 2019
Yesterday, Avnet announced the Ultra96-V2 as a replacement for the Ultra96 which is going EOL. https:/
ews.avnet.com/press-release/avnet/avnet-introduces-ultra96-v2-development-board     While Ultra96-V2 has the same Xilinx Zynq UltraScale+ MPSoC device, same 96Boards CE form factor, and the same basic features, there are several key differences which I thought would be useful to explain. Microchip Wi-Fi / BLE 5 Pre-certified in 75+ countries, including several where Ultra96 was ...
Note: The v1.0 Ultra96 board definition files (BDF) embedded in Vivado 2018.1 and 2018.2 have a bug. The latest BDF is on the Avnet GitHub here: https://github.com/Avnet/bdf . The article below describes the parameters included in the v1.2 board definition file.   The Avnet Ultra96 board from Avnet has 2 GB of LPDDR4 RAM that is interfaced to the Zynq UltraScale+ MPSoC's Processing System (PS) DDR Controller. This versatile controller is described in Chapter 17 of the ZU+ Technical Referen ...
Question: How did Avnet arrive at the DDR Delay values published in the MiniZed board definition file?   That's a good question! We developed the MiniZed board definition file with Vivado 2016.4. The settings you will find in the Avnet MiniZed board definition/awareness preset.xml are: Calculating these requires you to know the routing length in millimeters for the DDR clocks, DQS, and DQ traces. For MiniZed, we publish this in the net length report. You need clock and strobe for each 8 bi ...

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