The DSP48 Primitive - Instantiating the DSP48 Behavioral inference has many advantages - relatively simple and compact code, works with signed and unsigned operands of any size, hides the intricacies of the DSP48 primitive from the user. It should definitely be the first choice when coding a DSP based design if it produces the desired results in terms of device utilization and clock speed. That's a big if, when things do not go as you want there isn't much you can do - fighting wi ...

The DSP48 Primitive - Behavioral Symmetric FIR Inference The DSP48 primitive has an optional preadder function, which can be used to compute things like PCOUT=PCIN+(A+D)*B, which when used for implementing symmetric or anti-symmetric FIRs can reduce the number of multipliers used in half. The following diagram shows how such a symmetric FIR is built using the case N=4, a symmetric FIR with 8 taps as an example: The forward data delay line is identical to the one for the non-sym ...

The DSP48 Primitive - Behavioral FIR Inference As mentioned earlier, the DSP48 primitive is an essential part of any signal processing FPGA design and in over 90% of cases it's either FIR like sums of products or complex multiplications. For this reason we will focus now on efficient implementation of Finite Impulse Response filters with DSP48s, which will also cover other cases where computation of sums of products is required like linear algebra matrix multiplication and convolutional n ...

The DSP48 Primitive This post will start a longer series dedicated to the DSP48 primitive, a MAC (multiply/accumulate) block which is the workhorse for any kind of signal processing design that requires lots of mathematical operations beyond simple additions or subtractions, which are well handled with fabric based implementations that use the dedicated carry chain primitives. The DSP48, of which there are multiple flavors, one for each Xilinx FPGA family, started as a signed 18x1 ...

Using the Carry-Save Adder, The Constant Coefficient Multiplier Multiplications in Xilinx FPGAs are done using DSP48s, which are primitives that consist of a 25x18 signed multiplier, a 25-bit preadder and a 48-bit postadder/accumulator. In UltraScale/UltraScale+ FPGA families the signed multiplier is 27x18 and the post adder has three inputs instead of just two. Depending on the FPGA size and family there are hundreds to thousands of such DSP48 primitives, that are able to do one multiply ...

Using the Carry-Save Adder, A Generic Adder Tree In this post I will show how to implement an efficient and generic adder tree, we need to compute the sum of N elements, where N can be any value. The numbers we add are also arbitrary precision fixed point values, all the same range but otherwise unconstrained. We can represent the input data as an unconstrained array of unconstrained SFIXED, which requires VHDL-2008 support - with Vivado we can synthesize and implement this but we ...

Using the Carry-Save Adder, Computing a Running Average I will show in the next few posts some design examples where using a 3-input carry-save adder instead of the normal 2-input ripple-carry adder makes a significant difference. The first example is a running average, where we have a stream of input samples and we want to compute a continuous running average every clock, as the average of the last N samples. In mathematical terms: y(n)=1/N*Sum(x(n-k)), k=0..N-1 As a firs ...

The Carry-Save Adder, two for the price of one This post is about buying two adders but paying only for one of them. When developing software the CPU and memory your code is running on is already paid for and there is little incentive to optimize your code to make it either smaller or faster. But as a hardware designer you literally pay for every LUT and FF in the FPGA you are using. If you could make your design smaller and faster you could do more with the same FPGA or you could ...

Counters, Adders and Accumulators One of the most common operation encountered in digital hardware design, especially for digital signal processing applications, is addition. This actually covers a large group of fundamental building blocks, like up/down binary counters, adders/subtractors, comparators, accumulators and so on. The signal types operated on can be IEEE.numeric_std SIGNED/UNSIGNED for integer operands, the user defined SFIXED introduced earlier, or the default VHDL-2008 type ...

The Universal MUX Building Block Part 3, the one with the Dutch Cocoa Box and the Ouroboros We have seen in the previous post that Vivado Synthesis is able to optimally infer a mux form behavioral code for multiplexers with up to 16 inputs, but beyond that not so much. The synthesis results are not bad but for high performance designs where every LUT and especially every logic level counts not bad is not good enough. So in this post I will present a solution to this problem, that ...

The Universal MUX Building Block Part 2 So the question is now what is the most efficient implementation for arbitrary size multiplexers one should expect? If the result the synthesis tools infers from behavioral code is equal or very close to this there is no need for a specialized MUX Building Block. If the difference is significant then there will be a definite need for such a block, especially for designs with large muxes and/or many of them. To simplify the analysis we will f ...

The Universal MUX Building Block The next example in the series of generic building blocks is a multiplexer. This is a combinatorial block - if we need pipelining we can always add that separately to keep it as generic as possible - with an input port I of N elements, an UNSIGNED SEL port and an output port O, which is one of the N elements of the input port I selected by SEL. We want of course the I and SEL ports to be unconstrained arrays. The most generic solution would be one with a g ...

Instantiating LUT6 Primitives Part 2 Today I will show a couple of examples where LUT6 primitive instantiations make sense. To keep things short and simple these are somewhat artificial examples but situations like these tend to show up all the time in hardware designs. Let's say we need a 48-input AND function. This can be coded very easily behaviorally, especially if we take advantage of the new VHDL-2008 features: library IEEE; use IEEE.STD_LOGIC_1164.all; entity WideAN ...

Instantiating LUT6 Primitives In the previous post we have already seen how to instantiate FPGA primitives, SRL16s in that case. The role of the synthesis tool is to take HDL behavioral code and translate it into a netlist of FPGA fundamental building blocks called primitives. This is very much like the software design flow, where a C compiler takes C code and produces machine code that a processor can execute. The same way a C compiler lets you embed assembly code into your C program, th ...

The Universal DELAY Building Block Part 2, the one with the cake In the last post I have introduced an example of a universal delay block that uses a behavioral implementation to create a reusable module that can be used to delay a signal by an arbitrary but fixed value. Both the delay size and its width are generic respectively unconstrained, which makes the design reusable. While the behavioral implementation is quite compact and elegant, the synthesis result is not always what we reall ...