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14 Posts authored by: Jan Cumps
This DIY instrument is a PWM generator with dead band support. It has 2 complementary outputs and supports dead time. It can safely drive a (GaN) half bridge.     Specifications  PWM with fixed frequency: 1.5625 MHz Duty cycle: 6 bits (64 steps) Dead band: 0 - 150 ns, 4 bits (16 steps of 10 ns) Duty cycle variable, controlled with scroll wheel Dead band programmable from a browser Duty cycle display on a progress bar in a browser     Design  This DIY ins ...
The next step in my Zynq and Pynq learning; get information from an FPGA design into the Linux part: a rotary decoder that can read the movement of a scroll wheel. The original blog post for Spartan 6 and Xilinx ISE Webpack: Rotary Encoders - Part 5: Capturing Input on an FPGA   In this design, the FPGA decodes movements of a rotary encoder. The value is then written to a memory mapped register, that can be read from the Linux side. I will read it from a Jupyter notebook.   ima ...
The goal of this blog series is to master the Xilinx Zynq. I'm using the PWM design of my previous posts, and now switch to the raw AXI memory map interface between ARM and FPGA. In the previous post, I used AXI GPIO, the first step to memory mapped interface between the Linux and FPGA parts. Now I'm using the pure memory map (MMIO).   There isn't a lot of difference between the previous blog and this one. In fact, the previous one was a little but easier to use. But this one is our st ...
I posted a series of FPGA blogs. They focus on the toolchains and steps to get a working design. A common theme in those articles is the VHDL source. Each time, it's a PWM generator. A specific kind of PWM block: it can generate complementary output signals, to drive a transistor half bridge.   In this post, I'm drilling into that VHDL part.     Why this PWM module with 2 outputs and dead time I wanted to use a relevant exercise that solves a common task in electronics: driv ...
The goal of this blog series is to master the Xilinx Zynq. I'm using the PWM design of my previous post and switch to AXI memory map interface between ARM and FPGA. I learned this from beacon_dave 's PYNQ-Z2 Workshop - AXI GPIO post.   ARM/Linux to FPGA interface: from GPIO to AXI memory mapped register  in the previous post, I made a PWM generator in VHDL for the Zynq. I used the ARM EMIO GPIO bus as the interface between ARM and FPGA fabric. This is a 64 bit bus. I used 8 bits ...
The goal of this blog series is to master the Xilinx Zynq. I'll try to build a PWM controller for a half bridge power design. I've made a PWM with dead time design for the Xilinx Spartan 6 FPGA in 2017. I'm now learning to design for Zynq (I got a Pynq-Z2 board from our balearicdynamics!). I use the 2017 Spartan 6 design as a starting point.     Goals for this post  I want to have that PWM VHDL design running on the Zynq, and be able to change the dead time and duty cycle fro ...
Instructions on how to add the Pynq-Z2 board to Vivado. This allows you to create projects and custom FPGA bit streams for it.   image source: customer action video after completing the instruction video of Cathal McCabe listed at the end of this post.   In the Vivado project creation wizard, there is a possibility to prime your design from a board definition. You don't need to find out what the exact FPGA is, and what hardware is available. There are more project preparation to ...
This post is a preparation for my attempt to generate VGA with a XuLA2 FPGA board. I'm generating an image file that I can upload to the board's SDRAM. The FPGA will read it from the RAM and convert it into a VGA image.   The example project for the VGA plug-in for the XuLA has an example image. The latest loader tool for the board (xsload 0.1.31) doesn't support the format of that file. There's an older version of the loader that supports it but doesn't want to run on my pc. Not to ...
I purchased a Xess XuLA2 FPGA kit a while ago. As preparation for a test with its VGA module , I'm trying out one of the utilities to automatically create pin mappings.   You can plug XuLA modules into several connectors. Based on your choice, you have to route your signals to the FPGA balls that are connected to the pins of that connector. And: Mapping FPGA pins to connector locations can be a dog.     I found out yesterday that there is a utility to perform this much dread ...
The XuLA2 standard runs on a 12 MHz clock. That's plenty for many things, but not enough for some designs. In my PWM with DeadBand  project, for instance, the effective signal frequency that the module outputs is halved for each bit of precision of the duty cycle register. If you want to have 256 steps between 0 and 100% duty cycle, you need 8-bit precision and your maximum PWM output frequency is 47 kHz. When you need higher PWM frequency with the same duty cycle granularity, you can ...
A PWM module for FPGAs that supports dead band. A VHDL project that generates two opposite PWM signals with a dead band. You can change the duty cycle with a rotary encoder. When you drive half-bridge designs, you need a control signal for both transistors in the circuit. These signals need to be each other's opposite, because you close one transistor when you drive the other. At the switching time, you introduce a tiny bit of dead time, to allow one transistor to properly shut before t ...
How to use a rotary encoder with the XuLA2 and the Spartan-6 FPGA. Another real world example: I'm checking if the Xess Rotary Encoder library works with the encoder I use in a GaN half-bridge design. TL;DR: yes it works Xess has a plug-in board with a rotary encoder. I'm not using that module (called a StickIt!) - but I'm using the sample project that comes with it.   StickIt!   Hat Shield Cape Wing. All names were taken except the coolest one. StickIt!s are tiny modules th ...
Let's try to do something real with the Xilinx Spartan-6 FPGA: write a set of data to an SD card.   To boost the FPGA skills, I'm refreshing theory and checking out some real designs. For a standalone XuLA2 board, talking to SD cards is a good practical example.   There's  a Micro SD slot on the XuLA2 models. The only other component you need is a spare Micro SD card.   Don't use an SD card with your marriage photo shoot on it. You'll very likely loose that when you t ...
I purchased a Xess XuLA2. It arrived this morning. This post is the story of my first steps     I have a little bit of experience with FPGAs. I learned digital electronics in the early-to-mid 80's. My VHDL skills are beginner level and I've worked with the Xilinx Spartan 6 and development tools. This is my experience to run a first design on the XuLA2 board   I have done training work with the Spartan 6 FPGA before. The Xilinx development environment is running on my lapto ...

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