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12 Posts authored by: John Beetem Top Member
Here is the new release 0.0r of XXICC.  I've been horrifically busy with work and family obligations over the last two years so I wasn't able to keep up with XXICC.  Also, 0.0r is a major release since it adds integer nets and operators to GCHD, and can now program Lattice iCE40 FPGAs using the open-source IceStorm tools.  So there was lots of testing and documentation updates.   XXICC (21st Century Co-design) is a not-for-profit research project which attempts to bring digi ...
This is the summary page for the XXICC (21st Century Co-design) project. XXICC was previously hosted at Google Code, which no longer accepts new projects or edits to existing projects.  xxicc.org now links to this page.   The latest XXICC release is XXICC (21st Century Co-design) release 0.0r    XXICC (21st Century Co-design) is a not-for-profit research project which attempts to bring digital hardware/software co-design into the 21st Century using an improved programming ...
Arachne-pnr by Cotton Seed (who also uses pseudonyms cseed and mian2zi3) is an open-source FPGA placement and routing tool for Lattice iCE40 FPGAs.  It's a companion to the open-source Project IceStorm by Clifford Wolf and Mathias Lasser, which has reverse-engineered the iCE40 bitstream. The usual design flow for IceStorm is to synthesize Verilog source code using Clifford Wolf's Yosys to produce a netlist in the form of a Berkeley Logic Interchange Format (BLIF) file.  Arachne-pnr p ...
Project IceStorm, by Clifford Wolf and Mathias Lasser, is an amazing project that has reverse-engineered the Lattice iCE40 FPGA's bitstream so that it's finally possible to write open-source FPGA design tools for a real FPGA.  I've been playing with IceStorm and its companion tool arachne-pnr (place & route) over the last few days and it's been loads of fun with very few problems.  I'm going to add IceStorm as a synthesis target for my XXICC (21st Century Co-design) project.  ...
Release 0.0q has been replaced by: XXICC (21st Century Co-design) release 0.0r   Here is the new release 0.0q of XXICC.  0.0q adds logic capacity to Flavia implementation and allows you to specify pull-up, pull-down, and keeper circuits for FPGA I/Os in all implementations.  The Flavia architecture is now more consistent across all implementations: see the Flavia chapter of The XXICC Anthology rev 0.0q which has an updated version of Flavia: the Free Logic Array. XXICC (21 ...
Update 28 June 2015: XXICC has been updated to XXICC (21st Century Co-design) release 0.0q Here is the release 0.0p of XXICC.  There is no rev 0.0o since the letter O looks too much like the digit 0.  0.0p adds a Flavia implementation for the Gadget Factory Papilio DUO board, which has a Xilinx Spartan-6 LX9 FPGA and an Arduino-compatible Atmel ATmega32U4.  Flavia 0.0p also adds pinout tables to map top-level ports and signal names to FPGA pins.  You can also specify pull- ...
Here is the new release 0.0n of XXICC, which adds Xilinx Spartan-6 Flavia implementations for the ValentF(x) LOGI-Pi board and LOGI-Bone.   XXICC (21st Century Co-design) is a not-for-profit research project which attempts to bring digital hardware/software co-design into the 21st Century using an improved programming language and a Reduced Software Complexity philosophy.  Its goal is to make it easier and more enjoyable to write and maintain digital hardware and software. XXICC is pr ...
Here is the new release 0.0m of XXICC.  There is no rev 0.0l since lower-case L looks like digit 1.  0.0m is primarily a maintenance release with bug fixes and improvements to usability.  In addition, Flavia: the Free Logic Array has a new implementation FlaviaP48 for the Papilio One 500K.  FlaviaP32 for the Papilio One 250K now lets you change the default 2 Hz "proof of concept" clock to whatever you like between 1 Hz and 32 MHz.   XXICC (21st Century Co-design) is a n ...
Abstract: This ’blog describes using a ValentF(x) LOGI-EDU board to make a 4-digit BCD (binary-coded decimal) counter using LOGI-EDU’s 4-digit seven-segment LED module.  I used both LOGI-Pi and LOGI-Bone FPGA boards to implement the BCD counter logic.   Disclaimer: This ’blog is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY.  Incorrect board connections and/or an incorrect FPGA bitstream could cause damage to an FPGA and/or its connecte ...
Abstract:  This ’blog describes my first experiments using a ValentF(x) LOGI-Pi FPGA board.  After a short overview of LOGI-Pi and its Xilinx Spartan-6 FPGA, we show how to download two examples.  The first is a pre-tested LED demo from ValentF(x) and the second is created from Verilog source code using Xilinx tools.   Disclaimer: This ’blog is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY.  Incorrect board connections and/or an inc ...
Abstract:  This ’blog describes my first experiments using a ValentF(x) LOGI-Bone FPGA board.  After a short overview of LOGI-Bone and its Xilinx Spartan-6 FPGA, we show how to download two examples.  The first is a pre-tested LED demo from ValentF(x) and the second is created from Verilog source code using Xilinx tools.   Disclaimer: This ’blog is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY.  Incorrect board connections and/or an ...
This ’blog is the first part of Chapter 12 of The XXICC Anthology rev 0.0k.  For more information on XXICC, see the ’blog post XXICC (21st Century Co-design) release 0.0m and XXICC’s home page: xxicc.org.   Update 15 November 2014:  XXICC release 0.0m adds a second Flavia implementation: FlaviaP48 for the Papilio One 500K.  Rev 0.0m also allows the user to set the Flavia clock frequency values from 1 Hz to 32 MHz instead being fixed at the 2 Hz "proof of c ...

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