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5 Posts authored by: lucie tozer Top Member

Ive been recently using an M74HC590 binary counter to capture some data from an opto-encoder and thought that since I'd modelled a basic binary counter into the FPGA, why don't I go the whole hog and model this real world component into it too and make a final blog post in this series.

 

Here's the front page and the pinout  in the datasheet for the M74HC590 that I'll be modelling:

datasheet.jpg

pinout.jpg

 

 

 

 

 

 

 

 

 

So we know what the inputs and outputs are of the device are but what about the way it functions internally? Well I looked through the datasheet and found a truth table that I could work things out from.

 

truthtable.jpg

 

 

Using this data, I made up the following Verilog file:

 

m75hc590v.png

 

 

 

 

 

 

 

 

 

 

As you can see Ive copied the pin labels etc.. and used nested if's to do most of the logic.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

m74symbol.jpg

 

 

 

Once were happy with the Verilog file, we generate the board symbol shown here. Theres the corresponding input pins and the output pins QA throught to QG are shown as a single wire representing the 8bit output bus.

 

 

 

 

 

In the following schematic, Ive added the symbol for the Verilog file and made some connections to it:

 

board.jpg

 

 

 

The CCKEN and G pins have been connected to an internal Ground and CCLR has been connecting to an internal voltage source (VCC). These could have been broken out to real pins on the DE0-NANO P0082 board and connected manually but I did it this way for simplicity.

 

The RCK and CCK pins have both been connected to a push button on the development board.

 

The QA - QG outputs have all been connected to the LED's on the development board and the RCO pin has been left unconnected for the time being. This output would be connected to another 8-bit counter if they were being cascaded into a 16-bit counter.

 

 

 

From here it was just a case of assigning the LED's and pushbutton to the correct pins and the device is ready to test. The video at the bottom of this shows the final programmed development board. Because the CCK and RCK pins were attached to a push button, simply pressing that button causes the device to count up press by press.

 

Heres the compiler summary for the above component, very few of the actual resources were used (in most cases less than 1%):

 

summary.jpg

 

 

Hopefully this gives an insight into how fpga's can be utilised by modelling existing components that we already know, this is the final blog post in this mini-series but I will be posting occasional updates of my progress on an rgb led matrix driver that Im working towards with the DE0-NANO. I intend to cheat a little bit to start with and initialise some registers with a test pattern while I work out how to drive the signal properly. Once that's done I can work backwards into a more complex design.

 

 

 

 

 

So far the DE0-NANO P0082 development board and the associated user guides have given me a basic overview on how to develop with FPGA's and introduced me to a simple Verilog HDL file. To move forwards in FPGA development I would need to learn more about Verilog HDL and while Terasic have done a great job creating resources that teaches the basics of development I wouldn't expect them to provide me with a full Verilog HDL learning resource and so I looked elsewhere.

 

The first resource I found on Google was at http://www.asic-world.com/verilog/index.html and so I spent some time looking through their tutorials and examples, as with most new things I'm learning I find it useful to learn the basics and take a few days break. When I come back to the subject I find myself more able to understand what I'd learn previously and also learn more as I go.

 

After having a few days break, I decided to alter the files for the bitstream I made in Part 3 of this blog series. My intention was to create an 8-bit counter that displays on the LED's and the ability to change the direction of counting when one of the user buttons are pressed. Here is my new board layout :

 

board.jpg

 

In the board layout you can see I kept the pll to provide the clock source, the simple_counter module now has an additional button input and Ive removed the multiplexer, choosing to output 8 bits from the counter bus straight to LED's.

 

Before we look at the Verilog file for the simple_counter component lets investigate that counter bus a little bit more in depth. The counter bus is a single trace here but its representing a 32 bit bus with 32 wires, so here we've connected wires 18,19,20,21,22,23,24 and 25 to LED's and left the others disconnected. Its possible to connect a consistent range of 8 wires from anywhere in this bus and the LED's will still show an 8 bit counter.

 

Whats really going on is that simple_counter actually outputs as a 32-bit counter on that bus and were selecting a range, if we select a range of 0,1,2,3,4,5,6 and 7 the counter will be running so fast as thats where the least significant bits are that we won't see the LED's change (they'll just appear constantly on) and if we select the range 24,25,26,27,28,29,30 and 31 the LED's will count too slowly this is because as we move up the range the speed of the bits changing becomes less frequent.

 

It's entirely possible to just get the simple_counter component to output an 8-bit bus rather than a 32-bit one and alter the pll to change its counting speed to one that would be more suitable but I just left this one in for well, who knows why I left it in, it was just there already I suppose!

 

Right lets look at the new Verlog HDL file:

 

simple_counter.jpg

 

I added an extra button input and a new register component. Registers are similar to variables only you declare the size in bits you would like that register to be. So reg [31:0] is like a 32 bit variable and reg[0:0] is a single bit which Im using here like a Boolean to keep track of the direction.

 

You'll notice a new section titled "initial begin" this is a place you can initialise the values of the registers at the beginning of the bitstream launching/simulating.

 

Notice that there's 2 "always" blocks. These are functions that run automatically when their conditions are met. so the statements in the "always @ (posedge BUTTON_1)" block between "begin" and "end" will run automatically whenever a new positive edge is detected on the button (ie. whenever the button is pressed or goes high).

 

Multiple "always" statements are allowed in a component and can all run simultaneously.

 

and thats it for today, see the video below to see this in action

 

 

  If your looking to get into FPGA development and have been following my blogs, this is probably the post that you should pay most attention to as it's likely to make clear the design process.

 

So far I've followed the quick start guide,  downloaded the recommended software and installed the demo bitstreams onto the deo-nano development board. For clarification, a bitstream (or bit stream) is the name of your compiled project that gets transferred onto the FPGA device.

 

Now it's time to follow the my-first-fpga guide to create my first ever FPGA project, its a foolproof step by step guide which takes us from the very beginning of making a project through to downloading that compiled project onto the deo-nano development board.

 

Forget any other software that comes with the board, all were interested in is the Altera Quartus2 design suite, this has everything we need including a compiler and hardware programmer. This one thing does it all.

 

Here's a quick run through of the steps used to develop an FPGA application:

 

1) Create a project with the wizard, giving it a name and telling it which FPGA you are using.

2) Add a Block Diagram/Schematic to the project (this is similar to a schematic editor on PCB design software where components can be added, moved and connected with wires)

3) The objects on the schematic are created by using a programming language called Verilog HDL, it has similarities to other programming languages.

4) Once an object has been created in Verilog HDL, it shows up as a symbol on the schematic. Wires can be connected between these objects using inputs and outputs described in the programming.

5) Symbols of input / output pins are created on the schematic to represent the physical pins to allow interaction with the real world. These can be connected to the inputs/outputs of our object.

6) The input/output pin symbols are given names, a pin planner allows us to point those names to the physical pins on the fpga.

7) Compile the project.

8) program the bitstream (the output of the compiler) onto the fpga

 

Ok, there are a couple of other bits but thats a general overview and hopefully it outlines the process that people new to FPGA's can understand. Its basically very similar to making a circuit diagram in a pcb design package. Where the components have internal functions defined by a programming language. Anybody who used Javabeans and played with the Beanbox will be very comfortable using this!

 

So lets first look at the Block Diagram/Schematic view

 

schem1.jpg

 

 

 

 

This is the completed schematic for my project, The object in the top right labelled "simple_counter" is an object that I made in Verilog HDL following an example whereas the other two main objects are pre-made objects that Altera provides (A wizard can help set them up and tailor them for your needs).

 

Coming out of the right hand side of "simple_counter" is a wire labelled "counter", Because the wires going into the left of the "counter_bus_mux" are also labelled "counter" these are all symbollically linked so its as if all of those wires are connected to each other.

 

The smaller objects labelled "CLOCK_50", "KEY[0]" and "LED[3..0]" are all symbollic of physical pins on the fpga, these get assign or mapped to real life pins later in the process.

 

 

 

 

 

 

vhdl.jpg

 

 

 

 

 

Here's the Verilog HDL code that went into making the "simple_counter" object in the schematic above, as you can see it has an input and a output described, you can see these displayed in the schematic above. Notice how the structure is similar to other programming languages and it's pretty easy to follow.

 

Once this object has been saved we can add it to the schematic and link other objects to it, the design suite draws the object for us, we don't need to do anything like that ourselves.

 

 

 

 

 

pinassign.jpg

 

 

 

 

 

 

 

 

Once our schematic is complete, its time to launch the Pin Planner. If you look at the table at the bottom of the Pin Planner under node names, we can see the names of the input/output pins in our schematic above. In the location box is where we assign the pin in the schematic to the desired pin on the physical FPGA. In this picture, I double clicked the location box for "CLOCK_50" and a drop down list of all of the pins on our fpga device appeared. I selected PIN_R8 which is a dedicated clock pin, so looking back at the schematic we can see that CLOCK_50 is going to be turned on and off by a clock source on the fpga.

 

 

 

 

 

 

 

 

 

 

 

pinassigncomplete.jpg

 

 

 

 

 

 

 

 

 

 

 

 

Heres the completed pin assignment. This can be opened up at anytime during the design process to assign new input/output pins.

 

 

 

 

 

 

 

 

 

 

 

 

Once this is done your project is finished and its simply a case of clicking the compile button, plugging the de0-nano into a USB port and copying the compiled bitstream program onto the fpga using the programmer in the design suite. I have included any pictures for the process as it really is simple and self explanatory. There are pictures and a step by step guide in the my-first-fpga document but I have included a picture of the compiler report that was generated:

 

compilereport.jpg

 

 

 

 

 

 

 

As you can see, very few of the fpga's resources were used to make this project.

 

 

 

 

 

 

 

 

 

I'm going to try and explain the schematic (and hopefully get it right).

1) An external clock source is fed into a PLL(phase locked loop) element. This takes a 50mhz clock which is pulsing this pin on/off and slows it down. The output of this PLL goes into the simple counter, the single output of this counter is symbolic of a 32bit bus. The counter element itself increments the 32bit bus like it would a 32bit variable. From that 32-bit bus, just 8 of those bits are fed into the "counter_bus_mux". Im not sure exactly how that part works but it takes the data from those 8-bits and converts it into 4bits then displays it onto 4 led's.

 

Hopefully I got that right, if not then please feel free to explain better in the comments below!!

 

Heres a quick video of the results of this project:

 

 

And that's it for today! Tomorrow Im going to go Lone Ranger and try to get this binary counter displaying on all 8 LED's rather than just 4 before I get bogged down reading the full user manual.

 

Oh! Maybe I should mention that I completed this project in under an hour, there appears to be a lot to it but realistically it was easier than I anticipated!!

This post covers my experiences working through the quick start guide and moving on from there.

 

Installing The Software

 

All of the required software can be downloaded from http://de0-nano.terasic.com/cd I was required to register at terasic.com to download their software. Downloading the terasic cd and other bits from there was as simple as downloading a regular file. There are links from there to the Altera website where I found the Quartus2 design suite. Of course I had to register with Altera too to download this software.

 

At the Altera website, there are 3 different packages you can choose from. There's a lite edition which includes support for the cyclone4 that we will be using, theres a web edition which I chose to download for the time being and there's a premium edition which includes a larger range of fpga's and requires people to purchase a license to use. The first 2 options don't require any such license.

 

The Altera software is available for Windows or Linux, usually I would use a Linux version when there's a choice but the Terasic software has some Windows .exe files only so since I'm learning a new technology I decided to make things easier on myself and boot up my trusty old copy of Windows XP, maybe once I'm more familiar with the device I'll move over to Linux with it.

 

The final part of installing the software was to install the USB Blaster Driver. This is the device driver that your PC uses to talk to the FPGA board, unfortunately the quick start guide doesn't run through how to do this. After some investigating I found that the driver is included in the Quartus2 software that was downloaded and there are instruction for how to install it here https://www.altera.com/support/support-resources/download/drivers/dri-index.html in particular its the "USB-Blaster Cable" links you want to follow.

 

(later on I also found instructions for installing the device driver in the "my first fpga" document)

 

Using The Demonstrations

 

The demonstrations that come with the Terasic cd are easy to install onto the board (once you have the driver installed!). Simply locate the relevant .bat file while the development board is connected to your pc and it flashes automatically, so all of this seems simple enough and were at the end of the quick start guide. I'll need to look further into the documentation to find out how to make such a mysterious .bat file!

 

The final part of that guides suggests reading the user manual on the cd to learn more, while looking for that I noticed another file in the same directory called "DE0-Nano_My_First_Fpga_v1.0.pdf" and so decided to take a look at that first. I'm sure glad I did!!

 

Moving On From The Quick Start Guide

 

my1stfpgafront.jpg

my1stfpgapage1.jpg

 

 

 

 

 

 

 

 

Page 1 of this guide really seems to put me at ease, it just explains the process of FPGA design in a simple to understand way. I suppose part of the difficulty of getting into a technology like FPGA's is the fear of the unknown and the assumption that it's going to be really complicated. To have the process explained in such a simplistic and clear way has taken away a lot of my apprehension.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

my1stfpgapage7.jpg

 

 

 

 

 

 

 

Page 7 describes what the rest of this guide is all about, its basically a complete step by step guide to making a project with the Quartus2 design suite, it teaches you how to create a counter which displays on the LED's of the development board. Once the project is finished it guides us through the whole compilation process and then shows us how to get this compiled project onto the FPGA development board itself so we can see it in action.

 

 

 

 

 

 

 

 

 

 

 

Thats as far as Ive got today, it's time to kill some aliens on XCOM2!!

 

Positive Comments

 

So far my experience with this development kit has been greatly enhanced by the documentation which is easy to follow and is filling me with confidence that I will be up and running with FPGA development faster than I originally thought.

 

Negative Comments

 

The only negative thing I could say is that there should be more explanation on where from and how to install the device driver in the getting started guide, its impossible to flash the demonstrations onto the development board without it.

 

Suggestions

 

The My-First-fpga guide seems to be the valuable document needed towards learning the foundations of how to develop for this board and is a great asset to Terasic. It would be a great advantage if this guide was included in a printed format with the development kit, if using a single monitor it's soon going to get frustrating switching screens to follow the guide. I also believe such a thing would make a useful quick reference manual for people to keep handy.

 

For now though it's lucky Ive got a tablet to work from!!

box.jpg

 

Recently I was selected to roadtest the terasIC DEO-NANO P0082 fpga development kit. My application was based around reviewing the P0082 for suitability as an entry level device to simplify the process of people wanting to explore fpga development for the first time.

 

As part of that roadtest application I offered to post regular blogs here in the fgpa group on element14 documenting my progress, this first post centered around the unboxing and first impressions.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

contentsout.jpg

 

The Box Contains:

            - P0082 development board

            - Mini USB cable

            - Quick start guide

            - Brochures for other products

 

I always like getting brochures for other products!!

 

 

 

 

 

 

 

 

 

 

 

 

 

guidefront.jpgguideback.jpg

 

Quick start guide

 

Page 1 has a picture of the P0082 development board with labels to highlight the specific components.

Page 2 contains a brief introduction and a list of relevant software you will need to install to develope with the P0082.

Page 3 is an overview of the pre-loaded demonstration and links of where to download further demonstrations.

Page 4 looks at a control panel demonstration and a system builder tool to enable quick development on the P0082 (I'd imagine a project setup wizard).

 

boardtop.jpgboardbottom.jpgboardside.jpg

 

The P0082 development board looks well made, comes with a clear acrylic protective top cover and has standoffs to raise the bottom of the board from the surface its stood on which is a nice touch. The main component of the board is an Altera Cyclone 4. From what I understand at the moment, the Altera fpga loses all of it's configuration when power is removed and re-configures itself using an external EEPROM. To the left hand side of the board there is an I2C EEPROM so I'm assuming that this is where your compiled program (is that what you call it?) is downloaded from your computer onto ready for the fpga to read upon next power up.

 

Positive Comments

 

The development kit looks reasonably well presented, the quickstart guide is easy to follow and gives me confidence that the product is a worthy contender as an introductory device to the world of fpga's

 

Negative comments

 

One of the pins for the external power header is slightly bent, this coupled with the box looking rather worn and the software cd's that are supposed to be included are missing leads me to think this is a pre-used kit. Keep in mind though that this product was sent as a roadtest product and not one that has been purchased as new. Luckily the software packages can be downloaded easily enough so the missing cd's aren't a huge problem. Fingers crossed the board does function, I'll find out in due time!!

(edit) *after a quick power-up test, the P0082 is working fine and preloaded with the flashing led demo.

 

 

bentpins.jpg

 

* Pictures taken with my new general purpose camera Canon EOS 750D

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