Skip navigation
1 2 3 Previous

FPGA Group

114 posts
Sorting and Searching Algorithms   Now that we went through a variety of VHDL design building blocks and we saw the techniques to create both generic, reusable and at the same time efficient (in terms of speed and area) designs, using either behavioral inference or primitive instantiations, it is time to put what we have learned in practice. We have already looked briefly at FIRs, Finite Impulse Response Filters in the context of introducing the DSP48 primitive, there is a lot more to be s ...
The DSP58 Primitive   Xilinx has recently announced a new 7nm FPGA family called Versal. Devices in this family will have an improved version of the UltraScale/UltraScale+ DSP48E2 primitive we just studied in the last posts. The new Versal primitive is called DSP58 and there are numerous improvements compared to the earlier DSP48.   First of all, the signed multiplier, which was 27x18 in DSP48 is now 27x24 and the 48-bit post-adder/accumulator is 58 bits, which is where the name of ...
The DSP48 Primitive - Complex multipliers   Traditionally a complex multiplication can be decomposed into four real multiplications and two additions:      x+i·y=(a+i·b)(c+i·s)=(a·c−b·s)+i·(a·s+b·c) where     i=√−1   This maps well into four DSP48s, including the two additions, which can use the post-adders and the DSP48 P cascades. The latency of a fully pipelined DSP48 implementation is fo ...
The DSP48 Primitive - Inferring larger multipliers   The DSP48E2 primitive contains a signed 27x18 multiplier, any signed multiplier up to this size can be implemented with just one such primitive. If we need larger multipliers we can achieve that with multiple DSP48s.   The way larger multipliers are built uses a feature of the DSP48 primitive in which the 48-bit dedicated P cascade output of one DSP48 is right shifted by 17 bits before being added to the partial product calculate ...
The DSP48 Primitive - Small Multiplications - Two For the Price of One   The DSP48E2 primitive contains a signed 27x18 multiplier, any signed multiplier up to this size can be implemented with just one such primitive. Unsigned multiplications are of course possible if you add a zero MSB bit to the operands and then treat them as signed but the largest unsigned multiplication that can be done that way with one DSP48E2 is 26x17.   When the operands are much smaller it becomes possib ...
From: https://thetinysynth.wordpress.com/ The Tiny Synth, with its synthesis core measuring only 1.5×1.5mm, is probably the smallest subtractive synthesizer out there. Based on the Artix7 device from the latest Xilinx FPGA family, it provides a total of seven oscillators, three LFOs (Low-Frequency Oscillators), two envelope generators, tremolo and vibrato effects and an SVF (Static Variable Filter) with resonance and frequency control. The Artix7 device, the core of The Tiny Synth.   ...
The DSP48 Primitive - Wide XOR Mode   The DSP48 primitive can be used for more than just multiply and accumulate. It can for example implement very wide XOR functions. Apart from the obvious ability of XORing two 48-bit operands using the A concatenated with B, or A:B and C inputs and producing a 48-bit result on the P output, or 48 XOR2 logic functions, it is also possible to implement 8 XOR12s, or 4 XOR24s, or 2 XOR48s or one XOR96 with a single DSP48E2. It is also possible to compute a ...
The DSP48 Primitive - Symmetric FIR with DSP48 Primitive Instantiations   We will now add the option of choosing between DSP48 inference or primitive instantiations to the symmetric FIR introduced in Post 22. It might make sense to review Post 22 and Post 23 before continuing.   We will use the same technique, the generic BEHAVIORAL can be set to TRUE or FALSE to select between the two implementations. This is very similar to the code used in Post 24, except that now we are using the ...
The DSP48 Primitive - FIR with DSP48 Primitive Instantiations   After a break I will be resuming my weekly posts on The Art of FPGA Design. In the last posts we started looking at the DSP48 primitive, essentially a signed 27x18 multiplier which also includes a 27-bit pre-adder and a 3-input 48-bit post-adder. In older FPGA families like the 7-series the multiplier is 25x18, the pre-adder is 25-bits and the 48-bit post-adder has only two inputs. The DSP48 primitive also includes a lot of p ...
bhfletcher

Introducing Ultra96-V2

Posted by bhfletcher element14 Team Mar 28, 2019
Yesterday, Avnet announced the Ultra96-V2 as a replacement for the Ultra96 which is going EOL. https:/
ews.avnet.com/press-release/avnet/avnet-introduces-ultra96-v2-development-board     While Ultra96-V2 has the same Xilinx Zynq UltraScale+ MPSoC device, same 96Boards CE form factor, and the same basic features, there are several key differences which I thought would be useful to explain. Microchip Wi-Fi / BLE 5 Pre-certified in 75+ countries, including several where Ultra96 was ...
Continuing from where I left off in Driving a Laptop LCD using an FPGA, I moved the 'TMDS to LVDS converter board' to perf board, and soldered the differential pairs from the LCD panel onto it. I used headers (to connect wires) for the connections between the converter board and FPGA's PMOD ports, but not that I think about it, it might have been better to solder the headers so that it could be plugged directly to a PMOD (or 2 PMODs) without using wires. This setup was more stable, since the ...
Disclaimer: I posted this project hoping that it would be interesting and useful.  However, it is provided "as is" with NO WARRANTY of any kind and if you connect it to an actual organ you must know what you're doing to avoid damage to the organ or to the tuner.  The user assumes all risk using this project with actual hardware.   As electronics gets smaller and higher density it becomes more difficult and often impossible to repair and/or modify electronic products.  In too ...
Here is the new release 0.1 of XXICC.  I was very busy with work and family obligations over the last few years so I wasn't able to keep up with XXICC as I would have liked.  0.1 is a major release since it adds n-bit integers (1-32 bits) to GalaxC and GCHD.  These changes touched a lot of code and documentation.  I've tested what I could, but with this many changes there are bound to be some undetected bugs.  Please report any you find in the comments below, especially ...
Those of you with long memories will remember the first blog about this board: Ultra cheap and Tiny FPGA Board   I've built up a couple of boards and got them running some very simple start up software and VHDL. The good news is that there are only two small bugs on the board, neither is too grim to fix.   Other E14 members (notably jancumps ) have been Roadtesting the MAX32660 which provides one half of the good stuff on this board. My approach to coding the processor is very dif ...
This is a continuation of my on going N64 HDMI project. The last post can be found here: The N64=>HDMI Conversion Project: Part 2   I apologize for the delay in my updates. I am a full time college student and my studies always come first. I hope to get some work on my project done over the winter break.   I do have some updates however!   Since my last post I have done research on the ins and outs of analog TV signals. This lead me to the conclusion that my analysis prior t ...

Filter Blog

By date: By tag: