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FPGA Group

158 posts
Avnet has recently published an update to their Zynq & Zynq UltraScale+ MPSOC Systems Guide.  With over 15 years of experience building SOMS for Xilinx FPGA and SoC devices, Avnet has helped countless companies get a jump start on their product development and get to market faster.     Avnet’s Ready-made SoC Modules Can Shorten Your Development Cycle Today’s quick time-to-market demands are forcing companies to rethink how they design, build, and deploy their pro ...
Hi all,   I've seen quite a few recent posts with people seeing USB 2.0 speeds / connectivity when using the MPSoC.  I wanted to let you know that after scouring the interwebz, I think I've pooled enough information together to try to help you with your issues. If you are already familiar with USB 3.0 and transceivers, you can skip to the end!  Or stick around, you might learn a thing or two!   As USB speeds have risen from the lowly 1.5Mbps to the great 5 Gbps that we see ...
Avnet has partnered with Adam Taylor to offer three FREE days of training to help you get started with Xilinx Embedded Design! These trainings include a mix of recorded lectures and hands-on labs with the Avnet MiniZed Development Board. The trainings are targeted at new users, so if you've wondered where to begin, this is the place!     The trainings are based on the Xilinx 2019.1 tools. We are aware that 2019.2 is now out, including Vitis. Hopefully we will update the trainings in ...
Introduction This project is a follow up from the previous project on porting the PYNQ framework to the ZC702 development board. In this article we will show how to leverage the xOpenCV framework in conjunction with the PYNQ framework  to implement a basic image processing pipeline on ZYNQ series FPGA SoC . The project will be developed on a ZC702 development board using a generic USB camera.   Now , we will look at developing an end to end system for resizing live video using the ...
Hi Everyone,   Avnet has just released the PetaLinux 2019.2 BSP for the Ultra96-V2 board:   This BSP includes working WiFi and access point to ease configuration for connecting to the user's WLAN.  Instructions for this can be found in the Ultra96-V2 Getting Started Guide.   This BSP also includes the logic pieces in the programmable logic (PL) fabric to allow it to be used as the basis for a Xilinx Vitis platform to allow users to create custom accelerators or experiment ...
On Feb 18th, 2020, Avnet announced the availability of an Industrial-temperature grade Ultra96-V2. https:/
ews.avnet.com/press-release/avnet/avnet-upgrades-ultra96-v2-single-board-computer-industrial-temperature   This was something we hinted at last year when Ultra96-V2 was first released. This was mentioned again in ctammann's blog that discussed a new heatsink design for Ultra96-V2: Thermal relief is critical - design example around Ultra96-V2   I wanted to share a few more det ...
dimiterk

Porting PYQN to ZC702

Posted by dimiterk Feb 11, 2020
In this project we will port the PYNQ framework to the ZC702 development board.  Introduction   The ZC702 is an official development board from Xilinx. This board sports a ZC7020 ZYNQ FPGA SoC. It comes with a number of peripherals including HDMI, CAN Bus, UART, embedded Digilent JTAG Programmer, Ethernet , SD card, USB host , I2C bus expander and a number of SMBUS enabled PMIC for monitoring the SoC rails.      PYNQ is a project by Xilinx that brings Python le ...
A key feature of Avnet's Ultra96-V2 board is its WiFi and Bluetooth connectivity that is made possible using the on-board ATWILC3000 module from Microchip. This module is IEEE 802.11 b/g
plus Bluetooth 5 LE and is certified in more than 75 countries globally.  The module provides SDIO (WiFi) and UART (Bluetooth) interfaces for connecting to the host processor and can achieve WiFi throughput of up to 46 Mbps UDP & 28 Mbps TCP/IP.  Though this is a very popular module that is used ...
The Xilinx Zynq UltraScale+ MPSoC device has an integrated Platform Management Unit or PMU. This PMU's functionality is described in Chapter 6 of Xilinx UG1085, Zynq UltraScale+ Device Technical Reference Manual. The PMU controls many things on the ZU+ device, including powering up and down the ZU+. The Ultra96-V2 incorporates an On/Off controller to interface between the on-board power regulators and the ZU+. This allows the ZU+, Power Button, and regulators to seamlessly work together to power ...
I wanted to create a quick post explaining a small trick I noticed in the build process that allowed me to efficiently complete a build for Vitis and the Xilinx ZCU104 development platform.  I learned that if you abuse a tool, you can still make it behave improperly!   Summary: Uncheck the Autoupdate checkbox during an Ubuntu 18.04.1 LTS install Make sure to check that the # of JOBS being called out does NOT exceed the # of cores assigned to your Virtual Machine   Details: I ...
Previous blogs: FPGA: Making Waves FPGA: Waves 2: Simple Sinewave FPGA: Waves 3: Computed Sinewave Oscillators FPGA: Waves: 4 Tinker, Taylor, Soldier, Sine FPGA: Waves: 5 CORDIC Sine FPGA: Waves 6: Reconstruction Filter FPGA: Waves 7: Random Sequence Generator   Introduction   In blog 5, I looked at computing a sine using a CORDIC method. It was implemented in an iterated bit-serial fashion in a bid to keep the hardware usage low, though it turned out to be more complex than ...
Previous blogs: FPGA: Making Waves FPGA: Waves 2: Simple Sinewave FPGA: Waves 3: Computed Sinewave Oscillators FPGA: Waves: 4 Tinker, Taylor, Soldier, Sine FPGA: Waves: 5 CORDIC Sine FPGA: Waves 6: Reconstruction Filter   Introduction   I have a small Brevia 2 development board from Lattice Semiconductor featuring one of their XP2-family FPGAs. I'm using it to explore, in a very simple, basic kind of way, digital signal generation and processing. These blogs aren't tutorial ...
Previous blogs:   FPGA: Making Waves FPGA: Waves 2: Simple Sinewave FPGA: Waves 3: Computed Sinewave Oscillators FPGA: Waves: 4 Tinker, Taylor, Soldier, Sine FPGA: Waves: 5 CORDIC Sine   Introduction   In the last blog, I looked at computing a sinewave using a CORDIC method. It was implemented in a iterated bit-serial fashion to keep the hardware usage low, though it turned out to be more complex than I had anticipated because of some of the fiddly control necessary.   ...
jc2048

FPGA: Waves: 5 CORDIC Sine

Posted by jc2048 Oct 25, 2019
Previous blogs: FPGA: Making Waves FPGA: Waves 2: Simple Sinewave FPGA: Waves 3: Computed Sinewave Oscillators FPGA: Waves: 4 Tinker, Taylor, Soldier, Sine   Introduction   I have a small Brevia 2 development board [1] from Lattice Semiconductor featuring one of their XP2-family FPGAs. I'm using it to explore, in a very simple, basic kind of way, digital signal generation and processing. These blogs aren't tutorials and there's no structured path to any of it: it's just me exper ...
Previous blogs:   FPGA: Making Waves FPGA: Waves 2: Simple Sinewave FPGA: Waves 3: Computed Sinewave Oscillators   Introduction   I have a small  (Brevia 2)  development board [1] from Lattice Semiconductor featuring one of their XP2-family FPGAs. I'm using it to explore, in a very simple, basic kind of way, digital signal generation and processing. These blogs aren't tutorials and there's no structured path to any of it: it's just me experimenting and trying things ...

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