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FPGA Group

123 posts
The DSP48 Primitive - Wide XOR Mode   The DSP48 primitive can be used for more than just multiply and accumulate. It can for example implement very wide XOR functions. Apart from the obvious ability of XORing two 48-bit operands using the A concatenated with B, or A:B and C inputs and producing a 48-bit result on the P output, or 48 XOR2 logic functions, it is also possible to implement 8 XOR12s, or 4 XOR24s, or 2 XOR48s or one XOR96 with a single DSP48E2. It is also possible to compute a ...
The DSP48 Primitive - Symmetric FIR with DSP48 Primitive Instantiations   We will now add the option of choosing between DSP48 inference or primitive instantiations to the symmetric FIR introduced in Post 22. It might make sense to review Post 22 and Post 23 before continuing.   We will use the same technique, the generic BEHAVIORAL can be set to TRUE or FALSE to select between the two implementations. This is very similar to the code used in Post 24, except that now we are using the ...
The DSP48 Primitive - FIR with DSP48 Primitive Instantiations   After a break I will be resuming my weekly posts on The Art of FPGA Design. In the last posts we started looking at the DSP48 primitive, essentially a signed 27x18 multiplier which also includes a 27-bit pre-adder and a 3-input 48-bit post-adder. In older FPGA families like the 7-series the multiplier is 25x18, the pre-adder is 25-bits and the 48-bit post-adder has only two inputs. The DSP48 primitive also includes a lot of p ...
bhfletcher

Introducing Ultra96-V2

Posted by bhfletcher element14 Team Mar 28, 2019
Yesterday, Avnet announced the Ultra96-V2 as a replacement for the Ultra96 which is going EOL. https:/
ews.avnet.com/press-release/avnet/avnet-introduces-ultra96-v2-development-board     While Ultra96-V2 has the same Xilinx Zynq UltraScale+ MPSoC device, same 96Boards CE form factor, and the same basic features, there are several key differences which I thought would be useful to explain. Microchip Wi-Fi / BLE 5 Pre-certified in 75+ countries, including several where Ultra96 was ...
Continuing from where I left off in Driving a Laptop LCD using an FPGA, I moved the 'TMDS to LVDS converter board' to perf board, and soldered the differential pairs from the LCD panel onto it. I used headers (to connect wires) for the connections between the converter board and FPGA's PMOD ports, but not that I think about it, it might have been better to solder the headers so that it could be plugged directly to a PMOD (or 2 PMODs) without using wires. This setup was more stable, since the ...
Disclaimer: I posted this project hoping that it would be interesting and useful.  However, it is provided "as is" with NO WARRANTY of any kind and if you connect it to an actual organ you must know what you're doing to avoid damage to the organ or to the tuner.  The user assumes all risk using this project with actual hardware.   As electronics gets smaller and higher density it becomes more difficult and often impossible to repair and/or modify electronic products.  In too ...
Here is the new release 0.1 of XXICC.  I was very busy with work and family obligations over the last few years so I wasn't able to keep up with XXICC as I would have liked.  0.1 is a major release since it adds n-bit integers (1-32 bits) to GalaxC and GCHD.  These changes touched a lot of code and documentation.  I've tested what I could, but with this many changes there are bound to be some undetected bugs.  Please report any you find in the comments below, especially ...
Those of you with long memories will remember the first blog about this board: Ultra cheap and Tiny FPGA Board   I've built up a couple of boards and got them running some very simple start up software and VHDL. The good news is that there are only two small bugs on the board, neither is too grim to fix.   Other E14 members (notably jancumps ) have been Roadtesting the MAX32660 which provides one half of the good stuff on this board. My approach to coding the processor is very dif ...
This is a continuation of my on going N64 HDMI project. The last post can be found here: The N64=>HDMI Conversion Project: Part 2   I apologize for the delay in my updates. I am a full time college student and my studies always come first. I hope to get some work on my project done over the winter break.   I do have some updates however!   Since my last post I have done research on the ins and outs of analog TV signals. This lead me to the conclusion that my analysis prior t ...
The DSP48 Primitive - Instantiating the DSP48  Behavioral inference has many advantages - relatively simple and compact code, works with signed and unsigned operands of any size, hides the intricacies of the DSP48 primitive from the user. It should definitely be the first choice when coding a DSP based design if it produces the desired results in terms of device utilization and clock speed.   That's a big if, when things do not go as you want there isn't much you can do - fighting wi ...
The DSP48 Primitive - Behavioral Symmetric FIR Inference  The DSP48 primitive has an optional preadder function, which can be used to compute things like PCOUT=PCIN+(A+D)*B, which when used for implementing symmetric or anti-symmetric FIRs can reduce the number of multipliers used in half.   The following diagram shows how such a symmetric FIR is built using the case N=4, a symmetric FIR with 8 taps as an example: The forward data delay line is identical to the one for the non-sym ...
The DSP48 Primitive - Behavioral FIR Inference  As mentioned earlier, the DSP48 primitive is an essential part of any signal processing FPGA design and in over 90% of cases it's either FIR like sums of products or complex multiplications. For this reason we will focus now on efficient implementation of Finite Impulse Response filters with DSP48s, which will also cover other cases where computation of sums of products is required like linear algebra matrix multiplication and convolutional n ...
The DSP48 Primitive  This post will start a longer series dedicated to the DSP48 primitive, a MAC (multiply/accumulate) block which is the workhorse for any kind of signal processing design that requires lots of mathematical operations beyond simple additions or subtractions, which are well handled with fabric based implementations that use the dedicated carry chain primitives.   The DSP48, of which there are multiple flavors, one for each Xilinx FPGA family, started as a signed 18x1 ...
Using the Carry-Save Adder, The Constant Coefficient Multiplier  Multiplications in Xilinx FPGAs are done using DSP48s, which are primitives that consist of a 25x18 signed multiplier, a 25-bit preadder and a 48-bit postadder/accumulator. In UltraScale/UltraScale+ FPGA families the signed multiplier is 27x18 and the post adder has three inputs instead of just two. Depending on the FPGA size and family there are hundreds to thousands of such DSP48 primitives, that are able to do one multiply ...
Using the Carry-Save Adder, A Generic Adder Tree  In this post I will show how to implement an efficient and generic adder tree, we need to compute the sum of N elements, where N can be any value. The numbers we add are also arbitrary precision fixed point values, all the same range but otherwise unconstrained.   We can represent the input data as an unconstrained array of unconstrained SFIXED, which requires VHDL-2008 support - with Vivado we can synthesize and implement this but we ...

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