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FPGA Group

160 posts
Previous blogs:   FPGA: Making Waves FPGA: Waves 2: Simple Sinewave FPGA: Waves 3: Computed Sinewave Oscillators   Introduction   I have a small  (Brevia 2)  development board [1] from Lattice Semiconductor featuring one of their XP2-family FPGAs. I'm using it to explore, in a very simple, basic kind of way, digital signal generation and processing. These blogs aren't tutorials and there's no structured path to any of it: it's just me experimenting and trying things ...
Previous blogs: FPGA: Making Waves FPGA: Waves 2: Simple Sinewave   Introduction   I have a small Brevia 2 development board [1] from Lattice Semiconductor featuring one of their XP2-family FPGAs. I'm using it to explore, in a very simple, basic kind of way, digital signal generation and processing. This isn't a tutorial, just me experimenting and trying things out. In the last blog I used one of the block memories in the FPGA as a look-up table in order to generate a sine w ...
FPGA is fun and easy to learn. Interfacing of Digilent Cmod S6 FPGA development board with 7 segment display. In this code 7 segment display is directly connected to FPGA but it can also be connected through BCD to 7 segment decoder to minimize the number of IO pins.   Demo:   Important Links: Cmod S6 Schematics: cmods6_sch.pdf Master UCF file: cmod_s6_master_ucf.zip Factory Loaded Example: cmods6_demo.zip Reference Manual for Factory Loaded Demo: reference-manual VHDL Syntax f ...
FPGA: Making Waves   Introduction   I have a small Brevia 2 development board [1] from Lattice Semiconductor featuring one of their XP2- family FPGAs. I'm using it to explore, in a very simple, basic kind of way, digital signal generation and processing. I'm using VHDL to describe the digital logic that I'm designing. In the last blog I described a simple circuit using a low-cost 12-bit SPI DAC from Microchip, an MCP4821. I tested it by throwing together some VHDL to drive the D ...
A couple months back, I decided to buy an Avnet Ultra96 V2 board and make something interesting.  The Ultra96 is a compact, inexpensive platform with some amazing capabilities. https://www.avnet.com/wps/portal/us/products
ew-product-introductions
pi/aes-ultra96-v2?CMP=AMER-296-ULTRA96V2-XLX-MKTO-ENL-TALK1-201909&mkt_tok=eyJpIjoiWm1Nek5UZGpZMkV6TlRZeCIsInQiOiJBbXRwNXRkNVRaRXdWdDRxYlwvV00yT1M1N3k2TmJKVzBtb0xLXC9yR1Z6XC8wcDRONXdBeUJOMWI0OVRxamxWd2pvMTI0dFRxZFVnM2RjY29pWTNucEtSMmF5KzFG ...
jc2048

FPGA: Making Waves

Posted by jc2048 Sep 1, 2019
    Introduction   I have a small Brevia 2 development board [1] from Lattice Semiconductor, with one of their XP2-family FPGAs on it, that I bought from Farnell a while back. Last year I got as far as doing these two blogs before getting distracted and going off in quite different directions.   Booards and Boojums: Lattice XP2 Brevia2 Board: Part 1 Booards and Boojums: Lattice XP2 Brevia2 Board: Part 2: Count Those LEDs!   It's time to have another play ...
1 Introduction 2 The plan 4 The Projects 4.1 Hello FPGA 4.2 Button powered LEDs 4.3 Counting/Blinking LEDs 4.4 Debouncing 4.5 Vector display graphics 4.6 Xmas light show 5 Final words 6 References 1 Introduction Lots of FPGAs have been offered for roadtesting, but I never applied to any because I felt intimidated by the complexity of the FPGAs and was not sure I would be able to properly roadtest them in a 2 months period. Luckily for me the E14  ...
I had a lot of interest in my giveaway for the Digilent CMOD S7 board, so I am offering another giveaway for 2 members who are interested in experimenting with a Spartan-6 FPGA. Let me tell you about the board first.   It's called the Cmod S6 -- a Breadboardable Spartan-6 FPGA Module.   It's small, featuring a 48-pin DIP form factor board built around a Xilinx Spartan 6 LX4 FPGA.   The board also includes a programming ROM, clock source, USB programming and data transfer circ ...
Sorting Networks - The Verification Problem   In the final post on this subject of parallel sorting using FPGAs I will talk about the difficult issue of how to verify that such a design actually works. That is when given a set of any N input numbers in any arbitrary order the design outputs them in ascending sorted order. There are two main verification strategies for hardware designs, based on formal proof and exhaustive testing. The first one uses logical mathematical methods to prove th ...
Sorting Networks - The results for the VHDL implementation of Batcher's sorting algorithm   So how good is this VHDL implementation of a parallel sorting network? Before we look at the results here are the two modules that were missing from the previous post, a generic DELAY module for elements to be sorted:   library ieee;   use ieee.std_logic_1164.ALL;   use work.SORTER_PKG.all;   entity DELAY is   generic(SIZE:INTEGER:=1);   port(CLK:in STD_LOGIC; ...
A couple of months back I received a ZC702 Xilinx development board from Randall after pitching an idea on how to build an embedded vision project. The board arrived a couple of weeks later (thank you Randall) and I started working on the steps to build an embedded vision application that targets real time lane detection. The main idea was to build a vision system capable of automatic lane detection. In a nutshell,  I wanted to build a custom vision application running on the FPGA fabric th ...
Sorting Networks - The VHDL implementation of Batcher's sorting algorithm   OK, enough with the preliminaries, it's time now for the real deal, how do we implement in an FPGA this parallel sorting network thing. The main design goals are creating a generic, reusable and efficient implementation. We want to be able to implement a sorting network of any size N with a single piece of code, we want to be able to sort all kinds of data, not just integers and we want something close in size to ...
Sorting Networks - The Batcher or odd-even mergesort sorting algorithm   Now that we have defined the FPGA design engineering problem - parallel sorting of a set of N items in one clock, that is one new sorting operation starting every clock - we need to chose a sorting algorithm.While ideal in terms of performance (number of compare-exchange operations respectively latency) optimal sorting networks are irregular and more importantly they cannot be generated programmatically for an arbitr ...
Sorting Networks   Sorting networks are an interesting and unsolved mathematical puzzle. They are quite different from the usual sorting algorithms one encounters in computer science like bubble sort, quick sort, merge sort, heap sort and so on. While sequential algorithms are generic, in the sense that they work on an input set of items of any size, their execution time grows with N, either as  O(N·log2N) for the fast algorithms or  O(N2) for the more trivial ones and the ...
Here is the new release 0.1a of XXICC.  Rev 0.1a adds the return statement to GCHD (GalaxC for Hardware Design) which allows a hardware module to return a value without using an output port.  Rev 0.1a also adds GCHD comparison operators missing from earlier releases: x < y, x <= y, x > y, and x >= y.  Rev 0.1a also fixes some bugs, mostly involving n-bit integers.   XXICC (21st Century Co-design) is a not-for-profit research project which attempts to bring digit ...

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