IC’s typically specify an accuracy range requirement for their power rails. For a very long time 5% was the norm. In a lot of cases that still stands true, but with higher performance, higher accuracy or higher power devices this requirement has pushed down to 3% or lower. In addition, limitations may be set on peak to peak noise, transient response requirements and more. So how do you design your system to meet these requirements?

 

Sources of Error

A good first step is understanding your sources of error and doing what you can to minimize them. For a design example, we are going to focus on meeting a 3% accuracy requirement on a core rail for an FPGA. In this example we are generating a 1V output requiring 3A of current. Your error sources can be broken up into two operating conditions, static and dynamic. Static sources are based on slow changing conditions during normal operation. Dynamic are error sources caused by large changes in operating conditions like transients (load steps). Under static operating conditions, the primary sources of error are power supply regulation and voltage ripple. Dynamic performance adds to that other variations such as transient droop and DC losses. Voltage ripple is the peak to peak variation you allow in your design based on the switching characteristics. The switching frequency, inductor characteristics and output capacitance characteristics all come into play when designing for your desired ripple. I won’t get into calculating that value here, but for our example we will use a target ripple variation of 0.5%.

 

Your power supply regulation error is actually the summation of several error sources. Some manufacturers will give a regulation accuracy, others will give a reference accuracy. You must read the datasheet to see what is provided and base your estimations on that information. More often than not, regulation accuracy tracks the internal reference accuracy. This accuracy is one of the contributing factors to the power supply regulation accuracy. You also have line regulation error (error created by variations to the input voltage) and load regulation error (error created by changes to the output load). These are typically very small, but still need to be factored in. Another source of error that often gets overlooked is the feedback resistor network. These resistors, used for setting the output voltage of an adjustable regulator, can contribute significant error into your system. The error created by the feedback resistors is represented by the equation here:

There is an app note available here that goes into detail on how this equation is derived if you would like to explore it – www.ti.com/litv/pdf/slva423

This diagram illustrates all of the error sources and how they combine to produce your total regulation error. The feedback resistors in this example are 0.1% accuracy. Using the equation above you can see how specifying lesser accuracy resistors can contribute significant error to your overall output.

You can see that just our regulation error without consideration of DC losses or transient response add up to 1.6%, leaving only 1.4% for other error sources. Take a look at the DC loss examples in the illustration. At low voltages even moderate current levels can create substantial DC losses either through filter beads or even through PCB traces.

Here is a model of a transient response. Note that your transient response has a lot to do with the equivalent series resistance (ESR) and the equivalent series inductance (ESL) of your capacitor network.

This diagram shows what happens to your output voltage during a load step. When the load current starts to increase you get an immediate drop across the ESL of your capacitor since the current through an inductor can’t change instantaneously. That voltage will then dip as the current increases based on the ESR of the capacitor. When the current stops increasing the voltage drop across the ESL will go away and your capacitor discharges. You see that the converter current (regulator output current) increases as the control loop catches up to the additional load requirement. The converter current will go higher than the load current as it provides current both to the load and to replenish the capacitors that were depleted during the load step. The capacitance network consists of your input and output bulk capacitance as well as your decoupling caps and board parasitics. Hopefully this illustration helps show why it is so important to design a complete decoupling network using low ESR devices.

 

Minimizing the Error

There are several things you can do to try and minimize your error. Use fixed output regulators which eliminate the feedback resistor error. Be sure to select devices that specify either output error or reference error of 1% or lower. Provide plenty of decoupling and bulk capacitance, using multiple devices in parallel to minimize ESR to minimize transient droops. Place your regulators as close as possible to their intended load and use wide traces or heavier copper weight to minimize impedance. Route your power planes carefully and avoid routing switching signals like clocks near or around your feedback loops. Be careful with current sense resistors and filter beads, be sure to calculate the voltage drop across their impedance at your expected load currents. Consider using regulators with remote sense, which detects the voltage at your load and can make adjustments to the output voltage to minimize error based on DC losses.

 

When designing to higher accuracy requirements be sure you take into account all of your error sources to try and avoid getting bitten when your prototypes come in. What techniques have you used to meet strict regulation requirements? Please feel free to provide additional suggestions or lessons learned from personal experiences below.