The converter is designed to deliver high current, up to 50 A, at point of load. You can bring the power to the PoL via high voltages (this design supports 36 to 75 V).
This takes care that you can use smaller copper traces because the current will never get above 2 A before conversion.
At the point of load, this voltage is converted to 1V (programmable between 0.5 and 1.5 V).
By putting the converter directly near the load, the part of your PCB that has to transport the high current can be kept short.
The loads that this converter is targeting (processors, ASICs, FPGAs) are very dynamic by nature.
They can suddenly request several Amps extra. And the 1 V output level doesn't leave much room for voltage drop and recovery artifacts.
The design that we have here is resilient to these big changes in demand.
To proof this, the evaluation board has the option to inject a fast rise/fall 8 A extra current draw (the slew rate is a fast 10 A/μs).
This is done by switching a 120 mΩ resistor in parallel with the output.
It adds and removes that 8.3 A to the current that you are already drawing from the converter.
One of the reasons why I wanted to show this part of the DC converter, even if it's not part of the core design, is because it uses a 555 timer.
Every time I spot one in a modern design, I feel the urge to blog.
Here, it's the CMOS variant LMC555 that can clock up to 3 MHz. It's configured for 1.3 kHz.
The timer is controlling a gate driver IC. That one drives a power MOSFET. When this FET is driven, it switches that extra load in parallel with your test load.
When it's not driven, only your test load is active.
This means that the current changes dynamically two times per cycle, giving a 2.6 kHz dynamic change frequency (the documentation says 2.5 kHz).
The measured duty cycle is 34% (33% in the documentation).
The 120 mΩ resistor is in reality a set of twelve 3W 40 mΩ resistors - two strings of six in parallel.
In a next post I'll show the behaviour of the converter when this sudden change of demand happens at its output.
|part 1: Design Overview|
|part 2: Current Doubler|
|part 3: Dynamic Test Load|
|Checking Out GaN Half-Bridge Power Stage: Texas Instruments LMG5200 - Part 1: Preview|