To explore the regulation capabilities of the SMU I performed a few tests to see how it behaved in voltage priority mode (VPM), current priority mode (CPM), and in the (voltage) modulation mode. Let's briefly explain what all this modes are. VPM is the standard operation mode of power supplies, in this mode, the SMU starts in constant voltage (CV) (i.e., the SMU control loop regulates the voltage), so there is very little voltage overshoot. The SMU stays in CV unless the current limit is hit, and if this happens, it switches to constant current (CC). This is not instantaneous and during the transition from CV to CC the current can overshoot. CPM works the opposite way, the SMU starts in CC, and if the voltage limits get hit, the voltage can overshoot as it transitions to CV.


In the modulation mode the SMU acts like a voltage amplifier. In this mode the SMU takes the signal that is fed into the back panel connectors MOD- and MOD+ and amplifies with a gain of either 0.5, 1 or 2.



Voltage priority mode


I used the instrument's arbitrary function generator to generate a 10 ms pulse sweep from -20 V to +20 V in 0.5 V steps under different fast transient response settings (FTR) and loads. 4 tests were performed:

  1. Open circuit, FTR off
  2. Open circuit, FTR on
  3. 8 Ω load, FTR off
  1. 8 Ω load, FTR on


Recordings are displayed in 2 different ways:

  1. As a voltage and current time series
  2. As time-stacked voltage time series



As expected FTR increased the regulation speed, but at the cost of minor overshoots under 8 Ω load. These overshoots appeared to vary across repetitions of the test. One relevant regulation "glitch" occurred in all tests during the first pulse, where it took the SMU ~2 ms to reach the set voltage. This issue even though, highly repeatable in all tests, did not occur when the sweep began with positive pulses (from +20 V to - 20V). Note also that there are current spikes in the open circuit tests, these are caused by the SMU's output capacitor.



Current Priority Mode


In a similar way I tested the SMU in CPM under a short and ~0.3 Ω while performing a pulsed sweep from -8 A to 8 A in 0.5 A steps. Note that there are no FTR settings in CPM.



In both test the current regulation performed fairly well, with the exception of some overshooting during the 0.5 A pulse.




CPM Load Regulation


To test load regulation capabilities I performed a stepped voltage sweep from 0 V to either 6 V or 20 V (depending on the tested current load) in 0.5 V steps. The stepped sweep was performed using the instrument's AFG capability, while the 1 ms load pulses were generated with an "improvised e-load" made of an n-FET load connected to an (external) AFG. 6 conditions were tested:

  1. Max current ~0.5 A, FTR off
  2. Max current ~0.5 A, FTR on
  3. Max current ~3 A, FTR off
  4. Max current ~3A, FTR on
  5. Max current ~8A, FTR off
  6. Max current ~8A, FTR off


In addition to the raw voltage and current time series and the time-stacked voltage time series, I also plotted the time-voltage-stacked time series to better visualize the voltage dip and voltage swell.





The results were all as expected, FTR reduced the regulation time and the deviation from the voltage setting, and the higher the current the bigger the dip and swell. Even though the test conditions were very extreme, as current switched from almost 0 to 0.5, 3 or 8A, these test still show us what we can expect under different load conditions.





To test the modulation mode I connected an external AFG to the MOD- and MOD+ back panel connectors. The AFG was set to generate sine waves of 10 Vpp at 1 Hz, 10 Hz, and 100 Hz. The SMU gain was set to 1 and a load of 4 Ω was connected to the output.


As it can be seen, the signal is sampled at 1 kHz. I also noticed that no low pass filtering is applied, so care must be taken to avoid aliasing. One minor issue that I found is that every 100 samples (or ms), one sample "steals" dwell time of the next sample. This can be seen in the 10 Hz plot at around 95 and 195 ms.