This blog is to document my attempt to build Jan and Peter's load. I'm trying to catch up with Jan, who is

currently way ahead of me, so I can start doing measurements.


Although I normally prepare blogs in full before posting them, this time, as an experiment, I'm going to do it

differently and blog as I go along, with the blog gradually accumulating (accreting?) over time. It will be a bit

rough-and-ready and unpolished, but perhaps give a better flavour of the process and maybe illuminate things that

Jan might have glossed over. As an example, I've already realised that some of the software side that must be

obvious to him is evidently very unobvious to me (me just being a hardware hack). Indeed, at the time of writing this, I

can't even get the software to compile, even though I'm starting from a complete project that works for Jan.


The main blog for the load is here. That's the primary source for information and I'll be referring to it quite a

lot for the circuits and the software.



Programmable Electronic Load


Last year, out of interest as to how the circuit would behave, I did a series of blogs where I simulated the servo

loop. They're here, in case you want to read them:


Programmable Electronic Load: Dynamic Behaviour: Part 1 Overview

Programmable Electronic Load: Dynamic Behaviour: Part 2 The Servo Loop

Programmable Electronic Load: Dynamic Behaviour: Part 3 Effect of Output Inductance

Programmable Electronic Load: Dynamic Behaviour: Part 4 Effect of Output Voltage Change


Programmable Electronic Load: Dynamic Behaviour: Part 5 Stability


Once I have the load working on the bench I'm going to return to those, redo the simulations for the op amp that

I'm actually using, and see how the simulations compare to reality. I'm also going to have a look at tuning the

loop to see if I can improve the transient performance and look in more detail at the trade off between dc

stability and the ac performance.


Starting Point


The processor board I'm going to be using is the TI MSP-EXP432E401Y LaunchPad. Previously I had been using (trying

to use) the black version of the MSP432P401R LaunchPad, but Jan wanted to move away from that as the preproduction

silicon was limiting the software.



I could have gone for the non-ethernet version, but Jan is using this particular board so that improves my chances

of getting the software to work, and having the ethernet didn't add too much to the cost. I also feel that

networking items of test equipment with ethernet feels much more comfortable than trying to work with USB, so that

appealed to me too, though initially I'll be running SCPI over the USB since I'll be following exactly what Jan is

doing. The processor board was free too - I bought it using the shopping basket I won in a recent Project14

competition (unfortunately a $100 shopping basket doesn't go far when you're buying for one of Jan's projects,

though I got all of the important bits I needed to finish the project).


One difference between me and Jan is going to be the op amp. I intended to buy the device he is using (LT1058) but

it's no longer stocked by Farnell in the UK, so instead I bought a LT1125. This part doesn't have such a low bias-

current spec (the input devices are BJTs rather than FETs, and the FETs are a thousand times better), but the

voltage-offset spec is better (which is generally the case), the GBP is higher (though the slew rate is slower)

and, most importantly, it fits on the pcb footprint (which isn't a very common one and limits the selection of op

amps that will directly fit without adaption).


First go at compiling the software


Since I last did anything with this, TI have moved CCS (Code Composer Studio) on to version 8. So first job was to

install that.


Then I used the resource manager to download and install the SDK for the MSP432 parts. As well as routines for

peripherals, etc, that also includes TI's RTOS.




Next thing was to download Jan's zip file, with the software project in it, and unzip it to a folder under the CCS

workspace directory.


Then I imported the project to CCS and tried to compile it. It failed as it couldn't find the RTOS bits it needed.


"Referenced project 'tirtos_builds_MSP_EXP432E401Y_release_ccs' does not exist in the workspace. Project

'MSP432_SCPI_ElectronicLoad' may not build as expected."


To get round that I imported the example project tirtos_builds_MSP_EXP432E401Y_release_css from the examples with

the SDK and compiled it. Having that in place got me past the error about the rtos components, but I now have the

error message:


"Buildfile generation error occurred..
Build-configuration 'com.ti.ccstudio.buildDefinitions.MSP432.Debug.482273457' does not exist in the referenced

project 'tirtos_builds_MSP_EXP432E401Y_release_ccs'. See 'Properties > Build > Dependencies' page to select an

existing build-configuration.
Build stopped.."


Some Progress


I got past that by selecting 'Show Build Settings...' on the Project menu, selecting 'Build', and then changing the

odd looking dependency that it couldn't find to 'Debug' from the drop-down menu that appears when you try to edit it.


Now it compiles ok (so I'm further on than I was before with the black board).


If I set that running  I get this:



not the best picture ever, but you get the idea. So Jan's code is running on my processor board and can talk to the

Sharp display.




This is how the ADC/DAC board currently looks. Last year, when I first built it, the 2.048V voltage reference chip was on back-order so I improvised a temporary replacement with a LT1009 (a 2.5V part) that I had so that I could try the board even if the voltages would be wrong. I now have the proper device for U2, so the next job is to remove the temporary parts and see if I can manage to solder it to the board.




Replacing the Reference


I took off the temporary reference. Now I'm faced with this



At first I thought Farnell had sold me the wrong part, but the code on the top of the package does match what it says in the datasheet, so I guess I need to adapt the package to fit the footprint. Luckily we're only using three of the pins, so I can bend the others out of the way. Maybe.




This is now appears to be a complete mess, though it's not quite as bad as it looks. The unused legs are actually pointing up at the camera rather than down at the board, so there's much more clearance around the three pins that are soldered than it looks. I now see this coming out of the reference (that's measured across the capacitor at the output of the reference) so it's quite close to 2.048V.



In the morning, when my eyes are rested, I'll clean it up a bit and then start looking at the DAC.


First Go at Running the DAC Board


I've now got the ADC-DAC board plugged into the back of the processor board (the LCD display is in the same position on the other side of the board).



Next step is to talk to the load so that I'm in a position to issue SCPI commands. To do that I'm using PuTTY and I've set it up in the way that Jan describes on the main load information blog. After a bit of confusion about which COM port I should be using (not unusual with Windows), I see this




that's the load responding to the 'who are you'?' command, so that means I have usable communication with the load and can start issuing instructions to Jan's software.


As a quick test, I've just tried sending test values to DAC A (known to SCPI as DAC1)


DEVE:DAC1 0   results in a voltage of 0.391mV at the output pins of the DAC-ADC board (that's the low end of our control range - ideally it would be zero)


DEVE:DAC1 #HFFFF  results in a voltage of 2.0421V (that's the high end - it's a 16-bit converter - and ideally it would be the reference voltage of 2.048V)


The only load is the meter. This isn't driving the analogue board yet.


So talking to the DAC works. That's really good progress (well done, Jan!) because I now have the minimum that I need to control the analogue part.


Here's the low end of DAC A output. I didn't measure all the values, just enough to get the shape of the curve.



So it limits, with a minimum value that's greater than zero, AND there's an offset (if you extended the line down it would be below 0mV at the DAC 0 setting).


Analogue Board Build


I'm still making progress, though it's a bit slow. I've now built the analogue board. Unfortunately, I got U4 the wrong way round so I've got to take it off again. Beware if you build one of these - don't make the same mistake I did. (The pin 1 indicator is a line of silkscreen running down the side of the pin but it's so close it looks like it was cropped back by the board manufacturer. I should have worked it out from the schematic but guessed instead and inevitably I got it wrong.)



I've now removed U4 and added the J1 to J4 connectors. To remove U4, I cut each leg with snips, lifted the detached centre

piece out and then cleaned up each pad with a soldering iron. I don't have a replacement, so for the moment I've put a wire

link across from ground to the track that goes to the gate of the small MOSFET to stop it disabling the loop.



I've had 12V on P1 and can see the 5V output from the regulator and the -5V generated by U2.


Output Board Build


Here's the current state of the output board with the power MOSFET on it.



I put this one together quickly with a soldering iron, but it's messy and won't be optimum for heat transfer. I did wonder if

the iron would manage it at all, but after a few seconds the solder paste started to flow (80W Weller and a big bit). It

proved difficult to fill all the holes (I didn't want to be heating the MOSFET for too long), though the ones under the

device are all solid. One major problem is that there's nothing to hold the device in place and it will tend to float up on

the solder, so I tacked it in place on the component side, flipped it over so the MOSFET was pressed against a piece of

fibreglass board (back of a piece of single-sided pcb sheet) to protect the bench top and then did the main soldering from

the back. Something that helps is that Jan has limited the copper area on the component side so the heat flows through from

the back and is then limited to a fairly small area around the component.


Jan gave me more than one board and I had to buy five of the MOSFETs (the MOQ), so I can experiment later with alternative

construction techniques (I'd like to try it with an underboard heater and hot-air tool, though I'm not very good with SMD

work - give me an ordinary soldering iron any day).


One thing to watch is the thermistor. Here's the bare board with the thermistor placed next to its pads.



There's a real danger of shorting one side or other of the thermistor to the MOSFET drain. I cut across the bottom of the

piece of copper that goes between the pads to isolate it and also did a continuity check after I'd soldered the thermistor to

check that it wasn't shorted to anything and that the thermistor resistance was around 10k (it was).


Next task is wiring everything together and see if it will control a current.


First Test


Here is the analogue board and the output board wired together on the bench. For now I've merely tacked on connections for

the MOSFET gate drive and the sense resistor coming back.



The input voltage comes from a 10-turn trim pot. The voltage derives from the 5V supply that comes out on the header.

It's not very easy to see in the photo but the pot is across a 1N4148 diode, so the range is approx 0 to 0.7V. I've got my

best meter (the Fluke) measuring that. On the output side I've got a cheap handheld meter measuring the current. That has a

400mA fuse on the low current ranges, so I've also got a series resistor so that the output current can't exceed the fuse

rating with the 5V supply that's supplying the output side. I'm starting off with low currents - that's partly because that

is the area Jan is currently looking at, but mostly because I don't have much heatsinking on the MOSFET.


It works ok. Here's the plot I get of output current vs input voltage. This was done by hand and the points on the plot are

all a bit arbitrary. (I need to get automated like Jan.)



Like Jan, I have an offset on the current, but it's much larger - it's around 11mA. Next task will be to look at that and see

where it's coming from.


Reminder of the part of the circuit I'm looking at



Here are some more measurements:



The blue curve is the input control voltage. This is measured at the end of the 100k summing resistor. This is telling the load what

current we want. The orange trace is the voltage on the end of the other 100k summing resistor - it's the voltage that comes

from the current-sense resistor after it has been amplified by the current-sense amplifier (which has a gain of -6.8). The

yellow curve is the (calculated) midway point between the two [note to self: I should measure this]. The yellow line is about

500uV above ground.


The green line is a calculated line. I've taken the current value, multiplied it by the sense resistor value to get a voltage,

and then multiplied it by the gain of the sense amplifier. It's where the orange line ought to be. Both lines have the same

slope, so there's nothing wrong with the gain of the sense amplifier, instead we have an offset of some sort. The two lines

are 4mV apart vertically, so if I divide that by 6.8, I get an offset of about 600uV at the input of the amplifier. It's

slightly higher than the offset at the summing node, but they're both of the same sort of order.


Next question is where is this coming from? The op amp I'm using is a precision bipolar one. The voltage offset should be

better than 140uV (that's the guaranteed maximum value, so it's very unlikely to be even that much - typ. figure is 30uV), so

that suggests it's more likely to be the bias currents and their offset. That offset is only in the nA region [30nA max - good

for a bipolar input], but with the 100k resistors used in the circuit, that translates to voltages up in the mV area.


So I have a plausible mechanism for what I'm seeing here. I could do more measurements, but I'm tempted just to lower the resistor

values around the current sense amplifier and see what happens.


I've replaced the 100k/680k resistors used to define the sense amplifier gain for 1k/6k8. That leaves the gain the same but the currents involved are now much larger than the bias currents and their offset and that should remove them as a factor (on the sense amplifer, that is - there will still be an offset from the same cause on the integrator).


Here are the measured results. I've put the original curve on there as a comparison.


I'm now in the very fortunate position that, as well as getting me down to the area below a milliamp on the output current, there is now a positive offset on the control voltage that looks like it more or less matches the DAC output floor which can only get to within 400uV of ground. If I'm lucky, that will enable the DAC to get the output current down to zero. I'll find out when I try it with the DAC.


Slow progress, but I've now done a bit more.


I've connected the DAC to the output board and taken some readings at the bottom end of the range.

[This is with the DAC/ADC board running from the 5V supply from the analogue board and not the supply from the processor board.]

Here is how it performs. Remember that the DAC is 16 bits, so the range of values is 0 to 65535.

Unfortunately I wasn't lucky and I still have a minimum current above zero where we hit the floor of the DAC output (it's not very

clear from the graph but the minimum current now measures 0.81mA).


The current isn't very stable and wanders around by about 100uA or so. I had a look at the DAC voltage where it reaches the

analogue board and it looks like this. That's for a DAC setting of 100.



Although it doesn't look very nice, much of it is high frequency noise that the loop can't follow anyway.


If I look at the output current (I'm measuring it with a x1 voltage probe across some resistors) I get this



That's with a resistance of 43.7 ohms (bit of an odd value - it's several resistors in parallel to get the dissipation up a

bit). The scope channel has an offset of 250mV applied to bring the signal down near the base line so I can increase the gain

and see the variation in more detail. One vertical division is 5mV and is equivalent to about 115uA. So that corresponds to

what I'm seeing on the ammeter as it fluctuates. The horizontal scale is 4s (yes, 4 seconds!) per division, so it's very low

frequency noise. It's in the region where flicker noise would dominate a conventional op amp's noise, so is that what I'm

looking at here?




I should be playing at being a great artist (PiCasso!) and here I am looking at Jan and Peter's load



Recently, Jan used an op-amp so that he could use a second DAC output to lift the zero level above the

bottom of the control DACs range (the op amp on the DAC's output doesn't manage to quite get all the

way down to 0V, which isn't too surprising).


I decided I'd do it a different way and simply offset the integrator. Here it is as a schematic



and here it is wired to the board



That lifts the voltage that the summing node is being compared to slightly above zero.

I adjusted it so that the cutoff comes around 400 on the DAC output. Here it is on a graph

That graph hides something important. When I was doing this before I was seeing the output wander

around by about 100uA and that effect is still present. So the graph is an estimation, by me watching

the meter, as to where the centre is. That's the reason it's so uncertain.


Here is what it looks like on the meter as it wobbles around.



I still think that it might possibly be the integrator integrating the low-frequency flicker noise

from the op amps and taking us on a random walk, but I don't have any real evidence for that at the



So it is possible to get the currents lower than the 0.8mA I originally had, but it's not particularly

useful at the bottom end, because of the way it meanders around, other than being able to get the

output down to zero.




I've been looking at this again and now understand a bit better what's going on with the current wandering around.

I've also started using LTSpice. That's because the op amp I chose is an LT1125. I'm not altogether proficient

with LTSpice, but I'm starting to get the hang of it.


Here's the circuit as I've set it up for looking at the open loop-response



The response looks like this



The solid lines are the amplitude response and the dotted lines the phase response. The line across at the -40dB level

is the input (a 10mV sine wave). That's not the load input, it's the signal that I'm driving the loop with at the point where

I've broken it. The load input is held at a level of 20mV - so the curves are the response at the bottom end of the output

current range. The curve is the response through to the output of the current sense amplifier - ie, all the way round

to the other side of the break.


Although the integrator rolls off the the higher frequency response, at low frequencies the open loop gain increases. A fair

amount of gain down at dc is necessary because the integrator amplifier has to amplify a small error voltage at its input

and produce a voltage that can drive the MOSFET. Unfortunately, the 1/f 'flicker' noise at the input of the op amp

increases below about 10Hz (it's pink noise and increases inversely to frequency), so gets amplified by that gain.


To satisfy myself that it is the flicker noise I decided to do a small experiment. I adjusted the load to give an output current

of around 600uA and captured the output on the 'scope. Here's the trace (the probe is across a 100R resistor in series

with the current output, so each 20mV vertical division is equivalent to 200uA).



I then soldered a 20M (2 x 10M in series) resistor across the integrator capacitor
and this was the result



The effect of the resistor is to cap the gain at frequencies below 1Hz, rather than let it continue increasing. It means the

very low frequency components of the noise don't get excessively amplified and we can see the result of that in the trace

where the 1Hz components are still there but the lower frequency components are reduced to a more natural level.


I called this an experiment because it's not really a solution to the problem. Having a good level of gain is necessary

both to get the output up to the MOSFET gate level and to close the loop with only a small error voltage at the summing junction.