20 Replies Latest reply on Mar 26, 2015 1:30 PM by michaelkellett

    Barriers to designing with FPGAs?

    psymon

      I am interested to obtain people's thoughts on what is stopping them diving into FPGAs. I have my own theories on this subject and will share these as this discussion develops.

       

      I look forward to hearing your views,

       

      Thanks in advance,

      Simon

        • Re: Barriers to designing with FPGAs?
          Christopher Stanton

          I haven't had any familiarity with FPGAs.

           

          This's partly because, apparently the software to use them effectively is all expensive and proprietary; there's no (decent?) open source, free software to get started with them.

           

          Also I haven't seen any examples of using them so I'm not sure how relevant they are to me and projects I do or want to do to consider them.

            • Re: Barriers to designing with FPGAs?
              psymon

              Hello Christopher,

               

              Thanks for replying. You are not alone, lots of people think the software is expensive and if you want to target high end FPGAs it can be however, you can get software which will allow you to target complex FPGAs for free. Altera, Xilinx and Lattice all provide free software to eliminate this barrier.

               

              Your second comment is also very common, because FPGAs are so flexible it can be difficult to decide what examples to create. I am looking to load some content in the next few weeks which will at least start people off in their journey in using FPGAs.

               

              cheers

              Simon

                • Re: Barriers to designing with FPGAs?
                  Christopher Stanton

                  Altera appear to have Quartus, which costs money?

                  Xilinix appears to require licensing, there's some comment on a free version or evanulation but it's not clear what the restrictions or limits are on that.

                  Lattice does appear to have a free license, but it's not clear what restrictions are on that, aside from locking it down to your MAC address

                   

                  I'm assuming that across these licenses you wouldn't be able to use it beyond for personal use. Looking into the details were all behind login pages, which currently stopped me looking into it further.

                    • Re: Barriers to designing with FPGAs?
                      michaelkellett

                      If you want to play FPGA you'll need to get over your logging in inhibitions

                       

                      There is free (as in beer) software and you can do quite  a lot with it.

                       

                      Once you start paying for software it does get quite expensive especially if you buy from a silicon independent source. But for starting there is no need at all to do this.

                       

                      There are reasons why the software is the way it is - in the beginning Xilinx offered the first FPGAs, one with 64 look up tables (LUTs) and one with 100  - now we have devices with 10E6 LUTs. The software was paid for and I may mis-remember but I think at that time  (20+ years ago) was a few thousand pounds. When Actel entered the market their software was up at the £20k level. As time passed it became apparent that 1) the software was a major part of the product and 2) very few customers were prepared to pay for it up front.

                      This resulted in the rather odd business model for FPGA companies where they give away or sell for peanuts a software product that you would normally expect to pay very serious money for (comparing with similar complexity software - at least £10k).

                       

                      I get the feeling that no one much likes this situation but it's where we are and it isn't going to change quickly unless some one has a really game changing new idea.

                       

                      John B (who will probably chip in himself) thinks that if the Silicon companies would open up a bit and allow third parties including open source people ready access to the necessary info then open source tools could emerge that would change the game. So far no one has done that.

                       

                      If you could indicate the kind of projects you do I'd be happy to pitch an FPGA at you (or not if I don't think one would be any use.)

                      FPGAs can do amazing stuff but it takes a lot longer to write the 'code'  (really should be 'design the logic') than software based people expect.

                       

                      (I'm away for the next few days so I won't respond till Monday - if anyone replies.)

                       

                      MK

                      • Re: Barriers to designing with FPGAs?
                        John Beetem

                        Christopher Stanton wrote:

                         

                        Altera appear to have Quartus, which costs money?

                        Xilinix appears to require licensing, there's some comment on a free version or evanulation but it's not clear what the restrictions or limits are on that.

                        Lattice does appear to have a free license, but it's not clear what restrictions are on that, aside from locking it down to your MAC address

                         

                        I'm assuming that across these licenses you wouldn't be able to use it beyond for personal use. Looking into the details were all behind login pages, which currently stopped me looking into it further.

                         

                        Xilinx, Altera, Lattice, and Actel (now part of MicroSemi) all have free-as-in-beer (FaiB) software for their smaller parts.  If you want to use their chips that cost $1000 and up you'll have to pay for the software, but for any chip you'd want to use for learning you can use the FaiB version.  The FaiB version may not have all the tools that the pay version has.  For example, Xilinx ChipScope is not available in ISE WebPack.  Also, you don't get any support with the FaiB tools other than on-line forums.

                         

                        You do need to register to download the software.  I think this is mostly to ensure that you have "signed" the end-user license agreement (EULA).  This is standard with any software that's not Free-as-in-Freedom or Free (Libre) Open-Source Software (FLOSS).

                         

                        I've done all my FPGA work for the last 15 years or more using the FaiB versions.  There's no restriction on using the FaiB software for personal, educational, not-for-profit, or commercial applications.  It's FaiB to remove a barrier to buying FPGA silicon, which is how an FPGA vendor makes money and pays for tool development.

                         

                        I don't have time right now to go into my "The FPGA is the poster-boy for Free-as-in-Freedom Software" speech.  I'll come back and give you some links.  For now, take a look at my 'blog Flavia: the Free Logic Array.

                         

                        I'll take a crack at answering "Why would I be interested in designing an FPGA"?  Very simple:

                        Have you ever wanted a custom digital chip for a project, but didn't have $1 million lying around to pay for fabricating it?   Well, an FPGA lets you do it for tens of dollars.

                        Wow.  It still blows my mind.  Wow.

                  • Re: Barriers to designing with FPGAs?
                    kas.lewis

                    I have tried before but the student team I was learning from was using proprietary material that was monotone. So no easy access to learning and presented in a boring fashion. that being said, even now there does not seem to be an easy way to learn the ABCs of FPGA, flashing an LED or other seemingly very simple steps that can be eventually put together to make a bigger project.

                     

                    I would like to see a simpler approach especially considering that so many people today can program in C, JAVA, C++, C# etc. Why can't we talk in terms of what people already know, functions, variables etc. I know they are not the same but if some comparisons can be drawn then atleast I can get a foot in the door, which I could not do before.

                     

                    Kas

                      • Re: Barriers to designing with FPGAs?
                        psymon

                        Hello Kas,

                         

                        Thanks for taking the time to reply. How does this sound, if I create a few blog posts which explained with screenshots how to create some simple designs and back these up with a Video showing you visually the same steps.


                        If you think there is a better way to serve up this material please let me know and I will look into how feasible it is to implement,


                        Simon

                          • Re: Barriers to designing with FPGAs?
                            kas.lewis

                            Hello Simon,

                             

                            Firstly sorry for the VERY slow response, for some reason I only saw your replay now. As for your proposal I think that would be very interesting and informative way to learn. This would be especially helpful if there was an explanation as to why things are done (code explanation) as opposed to just showing steps. If there was an analagy to C or other more main stream programing as the tutorials went along it may be helpful as well.

                             

                            Kas

                        • Re: Barriers to designing with FPGAs?
                          D_Hersey


                          I feel that FPGAs are a solution seeking a problem to a certain extent.  It is a law of commodities that the first sip has the greatest worth.  Making them bigger and bigger when they are already really big doesn't seem to make them much more useful.  They would be fun if there wasn't the barrier of the software.  IRL, for most common problems, they are just too much.  They are marketed in a turgid manner; show me useful apps, not teabag me with fun fax about how this year's model is 4x more capacious than last year's model.  Just after they first came out I plunked a half K for an entry-level programmer (I was willing to do the high-level programming on graph paper and xeroxes from the databook with a pencil) for replacing jellybeans.  Lattice changed their chip, my programmer was now worthless.  Xeltek told me to cheer up and send them a further K!  This really soured me on the idea that these cats would do a small fry such as myself any justice.  The eeprom-based units of today obviate the need for a unique programmer, but seems to do nothing for the bureaucracies that decide that they really don't care about us.  Then after years and years these factors wonder why they have been unable to develop a user community!

                           

                          I was at a dinner party recently with a woman who has worked for decades for a major e- distributor.  She insisted that most sales are to govt's and institutions, major corporations, commodity parts.  Their interest in things like dev boards and the 'make' community they saw as something to entertain themselves while they waited for Hitachi's check to arrive for that last truckload of electrolytic capacitors.

                           

                          Hers is the largest corporation in Arizona.  There is no way they care about your hundred-dollar one-off dev board in any real, economic sense.  Their attitude is 'good luck, smartie!'

                           

                          ===========

                           

                          Also if your logic needs are combinatorial rather than sequential, and your number of inputs is similar to your number of outputs, you can use some kind of ROM as an LUT, as an alternative.

                            • Re: Barriers to designing with FPGAs?
                              mjonesvfx

                              Xilinx Wepack usage


                              Webpack ise is free to use for small to mid-grade chips.  The high end chips require a full license.  See the webpack software matrix can be found here, which shows any limitations to the webpack vs full versions.


                              Webpack is free to use commercially.  Here is a discussion where Xilinx’s motives are stated.


                              Altera also has a quartus web edition that is free to use and it appears to have the same un-limited structure until using large devices.  See the comparison chart here.


                              Though, it is free, it is bulky and not open.  John B. has started a great project which is moving in the right direction to opening things up to open tools. 


                              Programming requirements of Xilinx FPGAs - no expensive programmers needed


                              Xilinx and Altera chips offer a very basic way to load the configuration files (bit streams) using a slave serial data stream.  The LOGI boards use the Raspberry Pi or Beaglebone to simply load a bitstream dynamically.  This makes it nice to dynamically have full control of a single bitstream or multiple bit streams being loaded based on changing needs of the system.  I see the Rpi or BBB as a very low cost programmer + very powerful coprocessor.


                              Alternatively there are some relatively low cost programmers from digilent inc (~$50)  that can be used interface with the FPGA using JTAG.

                            • Re: Barriers to designing with FPGAs?
                              jpiat

                              Hi,

                               

                              This is a very interesting question.   With ValentFX we try to smoothen the learning curve for existing micro-controller/micro-processor users to begin to use FPGAs.

                               

                              One simple solution that we are pursuing is an online system-level edition of FPGA architecture (www.valentfx.com/skeleton). The user can create a hardware architecture using existing open-source IP (hardware components) represented by grapical components and then generate the corresponding top-level architecture and project for Xilinx ISE. For Linux users, the tool also generates a Makefile that can call Xilinx tools with no need to open the Xilinx ISE GUI.

                               

                              While this is not enough for someone to learn to design hardware, it is one way to get non-hdl developers  started doing things before they need to learn all the associated concepts of digital hardware design.

                               

                              Because we want our users to get their hands dirty and learn to write HDL we have started to experiment with alternative languages for HDL. The result of our experiments will be in a blog post we plan to post soon (sometime next week). We tested PSHDL and MyHDL that propose two different approaches for hardware design and they both work very well. The only thing is that i'am still not convinced that they are entry-level languages because they require to master quite a lot of concepts (especially MyHDL). I personally use VHDL and when testing those language i tend to map the VHDL construct to the MyHDL/PSHDL languages, and i would be interested to get beginners’ feedback on these or other languages. Testing those tools allowed us to define a proposed HDL language with the features one might expect and be comfortable with for a language to begin developing HDL.

                               

                              Proposed HDL Language Attributes

                              - Based on well adopted syntax so users can takes advantage of existing editors features (auto-completion, syntax highlighting, ...)

                              - Remove as much syntactical noise as possible. The user should not have to explicitly define what can be inferred from its constructions

                              - User should be able to write a basic example in just a few lines and clicks (three clicks should be enough to run a small example)

                              - An architecture can be defined in a single file (ease sharing) and with no need to define a complicated project structure (Arduino does this really well for micro-controllers)

                               

                              - Should be vendor agnostic …

                               

                              What features would you expect from a entry-level HDL Language?

                               

                              Regards,

                               

                              Jonathan Piat

                              CTO of ValentFX, Co-Counder of the LOGI-Boards

                              • Re: Barriers to designing with FPGAs?
                                John Beetem

                                Here’s what I see as the main barriers to getting people to play with FPGAs.

                                 

                                1.  “Logic!  Why don’t they teach logic in these schools?” asks the Old Professor in The Lion, the Witch, and the Wardrobe.  Well, they didn’t teach logic when I was in USA schools.  It was something you had to learn on your own.  I see no evidence that they’re teaching it now.  I don’t know about other countries.

                                 

                                Schools teach algebra, so you’re in better shape for computer programming.  But symbolic logic is the basis of FPGA design, so if you have to learn it at the same time that you’re trying to absorb the rest of FPGA design the learning curve is that much steeper.

                                 

                                2.  Verilog and VHDL are pretty much the only game in town for designing FPGAs.  The problem is that both are languages for describing hardware behavior and rather than the hardware itself.  If you’re an accomplished hardware designer, you know what registers and memories you want and what logical and arithmetic functions you want.  But to get a synthesizer to generate that hardware you have to write your Verilog or VHDL in just the right way so that the synthesizer recognizes pre-defined patterns for edge-triggered registers, clocked latches, and memories.  If you get the pattern wrong, the synthesizer will try to implement what you wrote but it will likely be a mess.  It’s usually hard or completely impractical to look at the netlist generated by the synthesizer so good luck untangling it.  If you’re a new designer, fuggeddabouddit.

                                 

                                At Design West / ESC 2013, Duane Benson gave a terrific talk called “FPGAs: I know nothing... yet” which covered a number of the challenges a new FPGA designer faces with Verilog.  It’s a great talk if you can find it online somewhere.  We had a recent discussion here at element14 called Connecting Verilog to Synthesis.  The OP had a design that simulated just fine but there were all sorts of problems when he tried to synthesize.  They can be very frustrating and discouraging for new users.

                                 

                                Here’s another recent example, this one from Gadget Factory: VHDL newbie: 'if' on a process sensitivity list element.  This new designer left some logic unspecified which caused the VHDL synthesizer to change combinational logic to clocked logic, and then gave an obscure error message about the user’s clock (which he didn’t realize he had).  VHDL calls every variable a signal and figures out at compile time which are combinational and which are registers, so if you make a mistake you can suddenly have unexpected added or missing registers.  In Verilog, you declare a variable as a wire or reg, which usually (but not always) prevents this particular problem.

                                 

                                I think those two discussions do a great job of illustrating the learning curve problem for VHDL and Verilog.

                                 

                                3.  FPGA tools have a steep learning curve.  If you want to write a C program, you start with “Hello, world” which is two lines of source code.  It takes one GNU command to compile it and one to execute it.

                                 

                                If you want a simple blinking light on an FPGA, you’re faced with the very long process of downloading the FPGA tools, getting the license manager to let you run the tools, figuring out how to use the tools, finally getting an FPGA bitstream, and writing it to your development board.

                                 

                                Plus the code itself is a lot more involved.  Blinking an LED sounds easy, but remember that your development board probably has a 32MHz or 50 MHz oscillator, so you need a clock divider to get it down to a few Hz.  Suddenly you need to learn about sequential logic and always or process statements.

                                 

                                We’re talking orders of magnitude more work than “Hello, world”.  OTOH, getting an LED to blink on a Raspberry Pi or BeagleBone is pretty involved too

                                 

                                Is there a better way?  You bet -- take a look at the examples at the end of Flavia: the Free Logic Array.

                                  • Re: Barriers to designing with FPGAs?
                                    John Beetem

                                    johnbeetem wrote:

                                     

                                    3.  FPGA tools have a steep learning curve.  If you want to write a C program, you start with “Hello, world” which is two lines of source code.  It takes one GNU command to compile it and one to execute it.

                                     

                                    If you want a simple blinking light on an FPGA, you’re faced with the very long process of downloading the FPGA tools, getting the license manager to let you run the tools, figuring out how to use the tools, finally getting an FPGA bitstream, and writing it to your development board.

                                     

                                    Plus the code itself is a lot more involved.  Blinking an LED sounds easy, but remember that your development board probably has a 32MHz or 50 MHz oscillator, so you need a clock divider to get it down to a few Hz.  Suddenly you need to learn about sequential logic and always or process statements.

                                     

                                    We’re talking orders of magnitude more work than “Hello, world”.  OTOH, getting an LED to blink on a Raspberry Pi or BeagleBone is pretty involved too

                                     

                                    Is there a better way?  You bet -- take a look at the examples at the end of Flavia: the Free Logic Array.

                                    In my continuing Quixotic quest towards making it easier for people to get started with FPGAs, the new release of Flavia (XXICC rev 0.0n) supports the ValentF(x) LOGI-Pi and LOGI-Bone.  Both boards have a Spartan-6 LX9 FPGA.

                                  • Re: Barriers to designing with FPGAs?
                                    tekmeister

                                    I love the potential of FPGAs (and CPLDs and other variations on the theme) and have used them in a previous job.

                                     

                                    I don't think the available development software is so much an issue. I can recall Quartus (and Max+Plus II) crashing a lot when I used them at university, but my recent experience has been OK. The software is often bulky and the lack of common terminology across different vendors can be confusing.

                                     

                                    For me the barriers are cost and power. These days I can pick up a MCU dev board for ~25USD, or a Raspberry Pi for ~35USD. A decent FPGA dev board costs an order of magnitude more.

                                     

                                    Also, it's typically not just the cost of the FPGA you need to worry about - you might want external ROM/RAM, regulators, etc.

                                     

                                    In its current state, the FPGA ecosystem (including the development tools) is geared for rapid prototyping or research, or very high-end products. The one-off costs aren't appealing for hobbyists, and the volume costs are prohibitive for low-margin products.

                                     

                                    Slightly off-topic: The PSoC is a fantastic concept, marrying a MCU with some FPGA-like capabilities. I'd love to use it in a commercial design, but unfortunately it is also hampered by its cost.

                                      • Re: Barriers to designing with FPGAs?
                                        John Beetem

                                        tekmeister wrote:

                                         

                                        For me the barriers are cost and power. These days I can pick up a MCU dev board for ~25USD, or a Raspberry Pi for ~35USD. A decent FPGA dev board costs an order of magnitude more.

                                        ...

                                        Slightly off-topic: The PSoC is a fantastic concept, marrying a MCU with some FPGA-like capabilities. I'd love to use it in a commercial design, but unfortunately it is also hampered by its cost.

                                         

                                        While FPGA development boards from FPGA vendors are often multi-hundred dollars, there are plenty of independent boards under US$100, such as the LOGI-Bone and LOGI-Pi.

                                         

                                        For lots of cheap FPGA development boards, take a look at Joel Williams’ list.

                                         

                                        The cheapest FPGA boards I’d consider include the $38 Papilio One with Xilinx Spartan-3E 250K, the $39 Gameduino (or similar Olimex MOD-VGA) with Spartan-3A 200K, or the $69 Xula2-LX9  with Spartan-6 LX9.

                                         

                                        I'm not sure why Spartan-6 LX9 boards cost so much more than 3E 250K or 3A 200K.  The FPGA chips now have the same prices.

                                         

                                        Regarding PSoC pricing: PSoC 5LP is pretty expensive, but you can get PSoC 4 chips for a couple dollars.  OTOH, you won’t get much (if any) programmable logic in those devices.

                                      • Re: Barriers to designing with FPGAs?
                                        Jan Cumps

                                        For me it's budget.

                                        Because an FPGA board is often more expensive than other development boards, I had to find some synergy.

                                         

                                        I circumvented my conscience by finding additional uses:

                                        - When I added the board (in my case one of the Papilio members) to my shopping cart, I went over the 'free shipping treshold'.

                                        - I'm using my FPGA board as a LogicSniffer compatible logic analyzer. That works particularly well for protocol analysis.

                                         

                                        IMG_3079.JPG

                                        • Re: Barriers to designing with FPGAs?
                                          mkr

                                          Not sure what the budget limit is, but the Zybo board is (in my humble opinion) a very interesting platform:

                                           

                                          http://digilentinc.com/Products/Detail.cfm?Prod=ZYBO

                                           

                                          Sure it's more expensive than Papilo, but you get three times the logic resources of Papilo Pro, a dual core Cortex A9 with sizable RAM and FLASH and quite a few interesting on-board peripherals - Gig Ethernet, HDMI, switches, buttons, leds, user-friendly expansion ports etc.

                                          • Re: Barriers to designing with FPGAs?
                                            takigama

                                            Thought I might add my own $0.02 to this. I've been interesting in FPGA's for as long as i could remember but never went down the path because it just seemed far to complex to get started in. But I always think of ASIC style operations when i think of FPGA.


                                            However, the complexity comes from where my interesting in FPGA's comes from, i've been a linux guy for as long linux has been, and i do storage/networking as my career. In those two area's (SAN/networking) theres alot of ASIC and the number of times in both of those area's where i've thought "if i understood FPGA's at all, there are so many idea's i've love to attempt/build" (though I cant say i was certain of how far an FPGA could really go). About a year ago a colleague who knew of my interest bought a really cheap one from somewhere and gave it to me as thanks for something. It was basically just an FPGA on a board with two leds, a switch and tonne of pin-outs but it got me interested in actually doing something, it took me the better part of a week to get the software i needed and to a point where i could control the leds with the button which I wont say dissuaded me from my end goals exactly but the sheer complexity of that task was certainly very daunting (and having done a reasonable amount of hobbiest type stuff with arduino and arm based MCU's it felt a little pointless).

                                             

                                            However, i made a goal for myself which was fairly ambitious to make a simple 2-port ethernet hub, extend it into a switch and ultimately aim for writing an entire network forwarding plane on an FPGA. I spent a bit of time figuring out the circuit i'd need to connect an rj45 ethernet to an FPGA and then more time again getting my head around the "core" i needed to drive a tripple-speed ethernet port directly off the FPGA (which later dumbed down into a 10baset only port) - the end result wasn't very encouraging, most of the core's were proprietary and licensed and completely indecipherable to me. However, the thing that eventually killed my interest (and i still dont really know) was getting an idea of what limitations/capabilities were on the FPGA i had when it came to that goal or even how i'd go about making a choice of FPGA with a goal in mind. Even googling was a little difficult, there seemed to be a lot of contradictory information out there and i also got the feeling that there wasnt many places a hobbyist focused FPGA enthusiast would be particularly welcome asking some really dumb questions. One example which was really aimed where I wanted to be was NetFPGA, seemed very welcoming to researchers but completely closed to hobbyists (though the cost behind their equipment ruled it out pretty quickly anyways).

                                              • Re: Barriers to designing with FPGAs?
                                                michaelkellett

                                                What FPGA do you have on your board ?

                                                 

                                                There are free Ethernet MACs around but the one I use is paid for. (hard to say how much (because of bundling) but about £500 per year.). You can use it for free indefinitely if you don't mind it switching itself off after an hour. (It comes from Lattice and only works on their FPGAs).

                                                 

                                                Big projects on FPGA are more expensive -  the chips are not cheap, a small FPGA will cost about £5, a mid range part about £100 and there is pretty much no top limit. The software is fairly expensive too - at the low end even the free simulators are OK but when you get on to big things then the prices rocket up. The chip vendors don't really sell software, they sell annual licenses  - not bad value if it's professional work but way out of hobby range.

                                                 

                                                Gbit Ethernet requires a high speed pcb which you would need to design and make or buy a ready made eval baord - there are some about and they can be found on promotional offers from Lattice, Xilinx or Altera from time to time - I paid $99 for one.

                                                 

                                                I think a Gbit ethernet switch is just about doable with free software tools so longs as you can get hold of hardware and the FPGA isn't too big for free tool versions.

                                                 

                                                As far as getting help on choosing chips and scoping projects you'll need to be thick skinned and ask in forums (fora ?). I've never found any books that are any good at that sort of thing. Although I use Lattice chips I think that Xilinx have the best support material on their website.

                                                 

                                                There is a lot of help on the web - but it's patchy.

                                                 

                                                Anyway - I'll be happy to help you get that board doing something if reasonably possible. (But I won't be able to help you with Verilog  - only VHDL.)

                                                 

                                                MK